Banked RAM cart

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brain
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Re: Banked RAM cart

Post by brain »

Mike wrote: Sun Jul 12, 2020 2:47 pm
brain wrote:So, since the IO range is 1kB, [...]
2 KB, but one would simply choose an arrangement of register map, transfer code buffer and boilerplate code buffer most suitable for the task.
I stand corrected. I hesitated to look it up, but laziness got the best of me
[...] whatever the fastest non unrolled loop option would be, what is the speedup per kB?
The math is easy enough. Regardless, non-unrolled is slower.
I'm in agreement unrolled is faster. But, since I am not a SW person, I figured I'd ask for the speedup. Looks like 2.3X or a bit better, or ~50K cycles for unrolled loop of 8kB and ~115K for normal. Still, that's 50ms versus 115mS, which is pretty marginal, all things considered. Just my opinion, of course...
That seems like a lot of uC code to write and debug for 3.5kB of RAM.
5 KB internal RAM for a stock VIC-20; or on a VIC-20 with VFLI mod, 8 KB internal RAM. When the file transfer method works there, it also works for expansion RAM ...
The expansion RAM code can be side-loaded by the uC without any lifting by the 6502.
... and, again, it would work the same way there, using standard KERNAL API calls and would not require programs to be adapted to the cartridge.
Hmm, not sure I understand that, because code isn't going to know about "just exec io2, and your data will get loaded into memory" and if it does know that much, it's easy to just change that to "exec io2, which will slow load the internal RAM and sideload the RAM on the cart".
Just wondering, as I'm game to try something, but it seems effort is more valuable in other spaces.
Well, you dismissed this idea already once, why should I expect you have changed your mind since then?
For a production unit, assuming this worked, I would offer both (an IEC pigtail for normal apps, and a conn to the CPLD for faster loading. I feel more comfortable.

Looking back at your rebuttal, I will admit your idea that the VIC-20 crowd would be OK without IEC support makes sense, given your argument in that thread. But, I even have PET folks complaining to me about disk-like features in sd2iec (since PetSD uses the sd2iec codebase), so I am just not comfortable that enough VIC-20 users will accept a device without IEC support, and I am just not willing to find out about that after I've committed to a product that does not have the support, as the community can be brutal (I know from experience)

But, that said, adding a sideload capability to a uC running sd2iec or similar is easier now than ever before, and your comments about fast loading of files from SD to memory makes a lot of sense.

Jim
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Re: Banked RAM cart

Post by TLovskog »

Just a comment from the person who suggested this way back.

The original idea was to create a cartridge with only a lot of SRAM. Decoding and configuration of read/write/enable would be done with cheap 74'series circuits. This logic in turn would be controlled by a really cheap PIC connected to the databus instead of FPGA/CPLD, and decoded to IO#2 or 3.

The setup/config program (or any other cartridges that you might want to have) would be loaded from FLASH in the MCU (programmed through USB).

After reset when the KERNAL looks for a cartridge at BLK5 (regardless of actually adress) the MCU would output to the databus the CBMA0 indication, startadress and then a series of LDA/STA for a very small boot loader. MCU then switched BLK5 to SRAM and the small boot loader would in a similar maner fetch the configuration program to SRAM via unrolled LDA/STA and execute.

This also evolved to instead of having LDA/STA pairs, having only one load for each available code needed with many stores scattered where needed. As in LDX #FIRST_NEEDED_CODE, STX $FIRST_NEEDED_ADRESS, STX $NEXT_NEEDED_ADRESS, INX (needed times), STX $THIS_CODES_FIRST_ADRESS, ...

Later I added SD card for all files with SPI connected to the MCU. Later also WiFi, and actually a IEC interface that was never tested.

There was also an idea to use this as a (slightly) faster move/copy/modify co-processor. In that case LDA $FROM, AND/OR/XOR, or nothing, STA $TO.

And then the project came to a grinding halt due to other work and family related stuff, as well as my inability to never stop looking for the absolut cheapest way to do this. In my daily work I always need to do things good enough. In my spare time I have the luxury of over engineering to my hearts content. The downside then, never completing.
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Re: Banked RAM cart

Post by Mike »

brain wrote:Hmm, not sure I understand that, because code isn't going to know about "just exec io2, and your data will get loaded into memory" and if it does know that much, it's easy to just change that to "exec io2, which will slow load the internal RAM and sideload the RAM on the cart".
User code is not supposed to have any business calling or accessing anything directly in the I/O area. The magic words in my preceding postings were: "[...] abstract from a bunch of different, incompatible register layouts for memory mapping. Instead standard KERNAL calls are used to move data between memory and files [...]", i.e. a wedge into all relevant KERNAL calls presents the standard API to all existing programs to operate with the new storage device driver.
I'm in agreement unrolled is faster. But, since I am not a SW person, I figured I'd ask for the speedup. Looks like 2.3X or a bit better, or ~50K cycles for unrolled loop of 8kB and ~115K for normal. Still, that's 50ms versus 115mS, which is pretty marginal, all things considered. Just my opinion, of course...
It is the difference between <10 frames/second and 25 frames/second, if the new file I/O method is used to stream video data into internal RAM for the VIC to display.
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Re: Banked RAM cart

Post by brain »

Mike wrote: Fri Jul 17, 2020 3:52 am
brain wrote:Hmm, not sure I understand that, because code isn't going to know about "just exec io2, and your data will get loaded into memory" and if it does know that much, it's easy to just change that to "exec io2, which will slow load the internal RAM and sideload the RAM on the cart".
User code is not supposed to have any business calling or accessing anything directly in the I/O area. The magic words in my preceding postings were: "[...] abstract from a bunch of different, incompatible register layouts for memory mapping. Instead standard KERNAL calls are used to move data between memory and files [...]", i.e. a wedge into all relevant KERNAL calls presents the standard API to all existing programs to operate with the new storage device driver.
My point is that your idea was stated thusly:

Code: Select all

For faster file I/O, what had been proposed in another thread - nearly 9 years ago - was a method that constructs transfer routines on the fly (most probably in I/Ox to keep RAMx and BLKx free for 'regular' code/data). A microcontroller would access the SD card in a known fashion, but not just providing a single register byte to load a byte from the file. Rather, when loading a file to memory (i.e. KERNAL load replacement/wedge), it would provide unrolled code in I/Ox like thus:

LDA #aa
STA $1001
LDA #bb
STA $1002
LDA #cc
STA $1003
[...]
I responded questioning the value of going to all effort, since it mainly would provide value to just the internal RAM only.

You commented "When the file transfer method works there, it also works for expansion RAM ..."

I questioned why you needed to do this method for expansion ram, since I could just load the expansion RAM directly from the uC

You then responded "... and, again, it would work the same way there, using standard KERNAL API calls and would not require programs to be adapted to the cartridge."

Which I don't agree with, but here's my full response, since it appears I am either misunderstanding things or you're misunderstanding my response.

IF we have a cart that one can access via std KERNAL routines, but that then populates IO2 or IO3 with unrolled code (as per your example), the code has to be executed from the on board 6502.
IF we assume that the KERNAL APIs are somehow patched or modified to know about the code that needs to be executed from IO2, then the application calls the KERNAL API, the API drives the registers on the cart, and the cart presents an unrolled loop of move instructions in IO2. The API then jumps to IO2 and starts running the code presented by the uC.

Now, if I am understand the above correctly (patched KERNAL APIs that know about executing code in IO2), something like this is the result:

IO2:
LDA #aa
STA $1001
LDA #bb
STA $1002
LDA #cc
STA $1003
[...]
RTS
#now in KERNAL API code
CHK_LOOP
LDA trigger_next_dump of code
BNE CHK_LOOP
JSR IO2 ; load in next chunk of code

Obviously, there needs to be a "are we done loading" check somewhere, where that's just details.

Now, if the above is the idea to load all the data, both internal and expansion RAM data, I was noting that without changing the API again or doing anything else, the uC could present the following code:

IO2
LDA #aa
STA $1001
LDA #bb
STA $1002
LDA #cc
STA $1003
[...]
; OK, we're done loading internal RAM, now to load external expansion RAM
LOOP
lda IO_REGISTER_TO SIGNAL_SIDELOADING_EXP_RAM
bne LOOP
rts

Since the uC is creating all the code, it can just as easily create the above chunk of code, which instructs the uC that the RAM is not being used so feel free to take it offline and sideload all the expansion RAM data needed, letting the 6502 know via the register when the uC is done. No more changes to KERNAL API other than the original change to allow the API to execute code in IO2

My point was not that USER code would know about IO2, but that the KERNAL API knows about IO2. And, if it knows about executing code in IO2, the uC need not resort to unrolling code to load the data into the expansion RAM via 6502 moves when it could just present code 6502 code to keep the CPU off the RAM, take the RAM offline, dump all the data into the RAM, and bring it back online.
I'm in agreement unrolled is faster. But, since I am not a SW person, I figured I'd ask for the speedup. Looks like 2.3X or a bit better, or ~50K cycles for unrolled loop of 8kB and ~115K for normal. Still, that's 50ms versus 115mS, which is pretty marginal, all things considered. Just my opinion, of course...
It is the difference between <10 frames/second and 25 frames/second, if the new file I/O method is used to stream video data into internal RAM for the VIC to display.
Mind you, if the position was that one could use bog standard KERNAL API codes to load from the cart and somehow execute this unrolled code in IO2, I am at a loss on how that would be done, since the KERNAL has no idea to jsr to IO2. I cna see it being possible if the "load" command loads a stub that then calls jsr IO2, but that only works for loads, not for opens and such. SO, if I assuming incorrectly about how the code in IO2 gets executed, I need more clarity.
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Re: Banked RAM cart

Post by pixel »

eslapion wrote: Sun Jul 12, 2020 2:03 am IMHO, I'm wondering why Pixel made that comment about making his own banked RAM cart and why he wouldn't simply buy an UltiMEM cart.
Got one already. And it's one of the hottest things one can plug into something with clothes on.
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Re: Banked RAM cart

Post by eslapion »

---
Last edited by eslapion on Fri Jul 31, 2020 4:55 am, edited 1 time in total.
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Re: Banked RAM cart

Post by Mike »

brain wrote:[...] if the position was that one could use bog standard KERNAL API codes to load from the cart and somehow execute this unrolled code in IO2, I am at a loss on how that would be done, [...]
That's exactly what the KERNAL vectors at $0314..$0333 are for, wedging into or replacing the relevant KERNAL routines.
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Re: Banked RAM cart

Post by pixel »

eslapion wrote: Sat Jul 18, 2020 12:14 pm Sidenote: You've still not read the PM I sent you.
Thanks, bro! Am confident that your suggestions for the ARUKANOIDO cart will do nicely. That game's gotta go out ASAP, so no extras should get in the way perhaps. The code looks like it's been written by some alien... :mrgreen: last round with the DOH (missing animations), little tweaks, done.
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Re: Banked RAM cart

Post by brain »

Mike wrote: Sun Jul 19, 2020 3:00 am
brain wrote:[...] if the position was that one could use bog standard KERNAL API codes to load from the cart and somehow execute this unrolled code in IO2, I am at a loss on how that would be done, [...]
That's exactly what the KERNAL vectors at $0314..$0333 are for, wedging into or replacing the relevant KERNAL routines.
I concur:
IF we assume that the KERNAL APIs are somehow patched or modified to know about the code that needs to be executed from IO2,...
You've provided the clarity that you expect the VIC-20 owner will have a machine with a patched KERNAL (via the the std KERNAL patch vectors).

I was a bit confused, as it appeared in earlier responses that you wanted to load all the expansion RAM using unrolled code executed by the 6502, and I see not reason to do that (just have the uC load the RAM directly), and your idea of using the 6502 via the KERNAL patch to exec code in IO2 means one can implement the unrolled code load *AND* the uC sideload without any further KERNAL mods or cart understanding beyond the original IO2 exec requirement.

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Re: Banked RAM cart

Post by Mike »

brain wrote:I was a bit confused, as it appeared in earlier responses that you wanted to load all the expansion RAM using unrolled code executed by the 6502, and I see not reason to do that [...]
The new routines for file I/O need in any case be able to access internal RAM, this is a strict requirement. And, it is preferable to make these transfer routines as fast as possible, for reasons I already stated.
[...] (just have the uC load the RAM directly), [...]
And again, if these routines work for internal RAM, they also work for external RAM. Having the uC on the cartridge pumping data directly to/from the external RAM adds further complexity to the setup and would not strictly be necessary. I would defer that feature to a second iteration of the firmware.
and your idea of using the 6502 via the KERNAL patch to exec code in IO2 means one can implement the unrolled code load *AND* the uC sideload without any further KERNAL mods or cart understanding beyond the original IO2 exec requirement.
I mentioned the word 'wedge' in just about every one of my posts here in this thread, and I took for granted the knowledge about how to extend the KERNAL.

To be clear about this: the new routines would only have the small window of I/O2 and I/O3 to work with. This is derived from another strict requirement: the new file I/O should be able to load into any other addresses than I/Ox - that means internal RAM [1], RAM1..3, BLK1..3, BLK5 - we'd expect the common user still be able to soft-load cartridges, no? :wink:

This small window will likely contain a very dynamic content. As different actions are necessary, the external uC would probably map one of a dozen different 2K pages (excluding the cartridge hardware registers) into I/Ox, some of them handling the KERNAL load replacement code, some other of them handling KERNAL save, etc. If you think this is rather complicated - it is likewise complicated to do programming in general with a RAM banking mechanism on application scale. And prone to programming errors, like banking out code that is part of an interrupt routine, by mistake (->crash). Better leave that complexity to the extended OS. :)

Putting these routines into service at power-on or on a 'hard' reset would temporarily map in code in BLK5 that is autostarted, inits the cartridge hardware registers and installs the new set of KERNAL vectors. When that is done, that 'cartridge' maps itself out. The new set of KERNAL vectors can be held active across STOP/RESTORE with a specially crafted NMI routine (similar to what MINIMON does with just the BRK and NMI vectors). A 'soft' reset should also be provided, which keeps the current cartridge register setup (especially, the current mapped in memory setup) and then starts any soft-loaded cartridges.

...

Well, this is still far away from being a blueprint, but should at least give an idea how I'd like to see this implemented. No low-hanging fruits anymore.

Greetings,

Michael


[1] including $0000..$03FF, though it's probably a bad idea to load into zeropage or other addresses currently used by the KERNAL to perform the load operation. But that's no different to throwing wrenches into a gearbox and would result in a similar outcome with the standard KERNAL routines.
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Re: Banked RAM cart

Post by TLovskog »

As an additional note,

Sideloading the cartridges SRAM from the uC directly would without doubt be quicker. Probably an order of magnitude.

However, it would require isolating the cartridge uC - SRAM bus from the VIC-20, and thus requiring additional electronics. The original idea I had 9 years ago was low cost. Also I wanted animations at startup in "hires", which required the cartridge to be able to write to internal SRAM as fast as possible.
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Re: Banked RAM cart

Post by brain »

TLovskog wrote: Sun Jul 19, 2020 12:55 pm As an additional note,

Sideloading the cartridges SRAM from the uC directly would without doubt be quicker. Probably an order of magnitude.

However, it would require isolating the cartridge uC - SRAM bus from the VIC-20, and thus requiring additional electronics. The original idea I had 9 years ago was low cost. Also I wanted animations at startup in "hires", which required the cartridge to be able to write to internal SRAM as fast as possible.
IN UltiMEM, I have to run the RAM through the CPLD because I use it as a way to convert the voltage levels. If you can "know" that the CPU is running by not accessing the RAM region, it would be trivial to switch the address and data lines to something else. And, I agree low cost is paramount, but I have found that throwing a CPLD on the PCB is the lowest cost option for a bunch of reasons, and once it is there, you can have these things "for free", so to speak.

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Re: Banked RAM cart

Post by brain »

Mike wrote: Sun Jul 19, 2020 11:11 am And again, if these routines work for internal RAM, they also work for external RAM. Having the uC on the cartridge pumping data directly to/from the external RAM adds further complexity to the setup and would not strictly be necessary. I would defer that feature to a second iteration of the firmware.
I appreciate your perspective, though I disagree. Pumping the data to the external RAM is trivia to me, and easy to track. Once you know the 6502 is not accessing the RAM, It's an address counter for the address lines, and a connection from 8 pins of the uC to the RAM.

The unrolled code stuffed into IO2 and all of the handshaking needed to support it is a lot of uC code and CPLD logic.

Need to bank into IO2 registers and some RAM to hold KERNAL wedge code
When KERNAL wedge code gets called (LOAD, for example), need to hold the 6502 in this code until another chunk of code with the unrolled data can be prepped by the uC, then swap. But, if all of that is in the SAME RAM IC, I have to interleave accesses to the RAM between uC (fast, probably 16MHz or 20MHz) and 6502 (slow, takes 500nS of every 1uS). You could optimize by waiting until halfway through the 500nS, grab the stable address, go fetch the SRAM data at that location, store it in a latch connected to the VIC data pins, and continue to allow the uC to have access to the RAM, but that's a lot of logic in itself.
Code to unroll the loop. Not too horrid to write, I'll admit, but more code.

So, in my mind, the easier path is to enable the sideload functionality in Rev 1, and then work on the uC unrolled code after.
I mentioned the word 'wedge' in just about every one of my posts here in this thread, and I took for granted the knowledge about how to extend the KERNAL.
Yes, I know about wedge code, and I knew KERNAL had to be modded to enable this. What tripped me up was your comments about not wanting the VIC to have to know about register changes between carts and such, which made no sense to me, because if you've already got the 6502 running code in IO2, then you can have that code do arbitrary things, including signalling the cart to sideload data, and since the cart put the code in IO2 to begin with, the wedge need not know whether it's running with a sideload cart or an unrolled code cart, or one that does both. I made the mistake of saying "user code", when I should have said "kernal wedge code" but I meant the latter. (TO me, it's user code, because I'm looking at it from the point of view of the uC. It's definitely not uC code.).
To be clear about this: the new routines would only have the small window of I/O2 and I/O3 to work with. This is derived from another strict requirement: the new file I/O should be able to load into any other addresses than I/Ox - that means internal RAM [1], RAM1..3, BLK1..3, BLK5 - we'd expect the common user still be able to soft-load cartridges, no? :wink:
Yes, all of the stuff has to fit in an IO area, and preferably 1 of them (I can see folks wanting to use this cart alongside another than uses another IO bank, like VIC-MIDI or some other expansion IO cart. So, I don't think it's good to tie both 2kB IO areas up.
This small window will likely contain a very dynamic content. As different actions are necessary, the external uC would probably map one of a dozen different 2K pages (excluding the cartridge hardware registers) into I/Ox, some of them handling the KERNAL load replacement code, some other of them handling KERNAL save, etc. If you think this is rather complicated - it is likewise complicated to do programming in general with a RAM banking mechanism on application scale. And prone to programming errors, like banking out code that is part of an interrupt routine, by mistake (->crash). Better leave that complexity to the extended OS. :)
on the HW side, banking is easy, but banking a single RAM while allowing a uC to write to said RAM at the same time it's being accessed by the VIC-20 is much harder. It's obviously doable, but my previous work in that area has been fraught with hard to debug corner cases. It's not a fun thing to do.

OK, so the idea is no longer the main topic. But, what is the target size? You got a uC, some logic (most likely and cheaply done by a CPLD), and RAM. Do we hold RESET low and skip ROM, using the uC to load some data into RAM on boot and then release RESET, mapping that RAM into BLK5 to auto-start? Or, is some FLASH ROM needed? If so, how much? How much RAM is ideal? Is there some size of RAM that makes sense if one of the targets is 15 FPS of video? B&W video @ 15FPS is 4096*15 = ~60K/second. But, one has to assume the uC is fast enough to read, unroll, save, and perform RAM housekeeping to keep up, so one should not need more than 2kB of SRAM to handle the video case. So, it mainly falls to expansion RAM needs for other uses. Is 2MB enough? There's an 8MB SRAM< but it's not cheap (I think $28/unit) On the other hand, 512kB SRAM is almost the smallest you can buy, and the prices reflect that. Maybe with an option to load data into RAM on demand from a uC reduces the need for large chunks of RAM.

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Re: Banked RAM cart

Post by Mike »

brain wrote:Yes, all of the stuff has to fit in an IO area, and preferably 1 of them (I can see folks wanting to use this cart alongside another than uses another IO bank, like VIC-MIDI or some other expansion IO cart. So, I don't think it's good to tie both 2kB IO areas up.
I think it's a futile attempt to operate two carts on the VIC-20 that both use the I/O area for registers. Even if the registers don't collide - the carts will very likely kick each other out of operation by kidnapping the KERNAL vectors or other resources.
on the HW side, banking is easy, but banking a single RAM while allowing a uC to write to said RAM at the same time it's being accessed by the VIC-20 is much harder. It's obviously doable, but my previous work in that area has been fraught with hard to debug corner cases. It's not a fun thing to do.
As I said, no more low-hanging fruits. I think we're done with simple bank-switching RAM expansions. They leave all the burden to the programmer. No support beyond raw paging in level data for games or replacing code with a 8 KB granularity. At the best, a RAM disk as has been implemented for the FE3 some years ago (with its rather inflexible Super-RAM mode, which only handles 4 BLK areas at once).
OK, so the idea is no longer the main topic. But, what is the target size? You got a uC, some logic (most likely and cheaply done by a CPLD),
... the SD card slot ...
and RAM. Do we hold RESET low and skip ROM, using the uC to load some data into RAM on boot and then release RESET, mapping that RAM into BLK5 to auto-start?
I think that's better done with a dedicated ROM (area), mapped in as necessary. A reset, regardless of what kind, should not tamper the RAM. There could be a soft-loaded cartridge in BLK5 RAM, which the user wants to start. See my previous post mentioning a 'soft' reset for this reason.
Or, is some FLASH ROM needed? If so, how much? How much RAM is ideal? Is there some size of RAM that makes sense if one of the targets is 15 FPS of video?
When data can be streamed from a SD card, the expansion RAM size becomes largely irrelevant. Of course the "full" RAM expansion of 32 KB (BLK1..3, BLK5) + 3 KB (RAM1..3) is the lower limit, anything beyond that is fine.

2 MB SRAM would have the nice aspect, that it would be exactly 256 8 KB chunks, so the banking mechanism for BLKx could be made atomic. As in UltiMem, $0400..$0FFF of each of those 8K blocks could alternatively be mapped in for RAMx.
B&W video @ 15FPS is 4096*15 = ~60K/second. But, one has to assume the uC is fast enough to read, unroll, save, and perform RAM housekeeping to keep up, so one should not need more than 2kB of SRAM to handle the video case. So, it mainly falls to expansion RAM needs for other uses. Is 2MB enough?
For RAM banking, probably yes. See above.

With the loop unrolling a transfer rate of 100 KB/s should easily be possible, which gives 25 fps (assuming a 4 KB MINIGRAFIK bitmap as graphics mode). The uC also should prepare the next 'page' of code while the 6502 churns along the current transfer code, otherwise a lot of speed is lost with the 6502 waiting for the uC to build the next chunk of transfer code.
There's an 8MB SRAM< but it's not cheap (I think $28/unit) On the other hand, 512kB SRAM is almost the smallest you can buy, and the prices reflect that. Maybe with an option to load data into RAM on demand from a uC reduces the need for large chunks of RAM.
Exactly. :wink:
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Re: Banked RAM cart

Post by Mike »

TLovskog wrote:As an additional note,

Sideloading the cartridges SRAM from the uC directly would without doubt be quicker. Probably an order of magnitude.

However, it would require isolating the cartridge uC - SRAM bus from the VIC-20, and thus requiring additional electronics. The original idea I had 9 years ago was low cost. Also I wanted animations at startup in "hires", which required the cartridge to be able to write to internal SRAM as fast as possible.
You see the bag of ideas/concepts I am unloading here in this thread. Now, *does* it in any way resemble what you got in your hands?

I could imagine to launch myself at a re-implementation of this fast SD card drive. But the perspective of having this attempt being turned into a waste of effort - in case you change your mind and actually release GCart 2011 - is what keeps me from actually starting it. :(
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