Homebrew: An alternative to a 6561 VIC Chip...?

[SparkyNZ]

Hi Everyone. I think my VIC chip is dead. I posted an article on here a few years back. Only just tried replacing UC2 (74LS04) and it's still the same. So tomorrow I'm going to give it one last go - I'm going to desolder the old VIC, add socket and see if the spare 6561 I have will work.

If all of this is a waste of time.. I'm just wondering how difficult it would be to substitute the VIC entirely with an FPGA homebrew project?

So just a few questions: Will a Vic 20 continue to run if the VIC chip isn't actually present? ie. is there a self-test of some sort that takes place at boot-up that would prevent the machine from booting to the BASIC interpreter?

I've ordered an FPGA development board to play around with generating VGA displays anyway. I'm just toying with the idea of being able to hook this up to the VIC data/address bus etc and doing my own display on VGA instead.

[SparkyNZ]

OK. As of today, I have confirmed that my 6561 is definitely dead. I have 3 PAL Vic-20 machines and only 1 with a working 6561 chip. I'm not going to pay for another 6561.

So.. I would like to have a go at creating my own (modern) video interface of sorts - substituting the job of the 6561. I'm already keen on doing a homebrew 6502 computer project anyway so this Vic mod could be quite interesting.

What exactly would I need to do to fool the rest of the Vic's chips that everything is up and running as normal?

1) I understand that pin 35 of the 6561 is a clock signal which the 6502 needs to cycle (?)
2) What exactly are the purposes of pins 38 and 39 (phase 2 and phase 1 clock inputs)

Assuming I can generate a clock signal (could I use an LMC555 timer perhaps??), feed that into pin 35 on the Vic socket, would the Vic actually start up and run the BASIC interpreter - even though there's no video implemented?

Reading this article here: http://tinyvga.com/6561

Does the timing "chain" work like this:

Crystal Oscillator -> 6561 -> pin 35 to 6502
6502 -> Feeds back alternating Phase 1 and Phase 2 signals back to 6561
6502 (Phase 1, pin 3) -> 6561, Vic enabled "Chip Enabled" and allowed to access RAM
6502 (Phase 2, pin 39) -> 6502 is Chip Enabled and allowed to access RAM

So within Phase 1, would there be both a read and write between the Vic and RAM, or would there only be 1 write in a Phase 1 cycle and perhaps 1 read in another Phase 1 cycle?

[eslapion]

I'm just wondering how difficult it would be to substitute the VIC entirely with an FPGA homebrew project?

lance ewing and the people participating in the thread he started are still busy figuring out what's inside the actual chip from microphotography.

They've been at it for a few years at this point. http://sleepingelephant.com/ipw-web/bul ... =11&t=8733

So just a few questions: Will a Vic 20 continue to run if the VIC chip isn't actually present?

Nope. The clock signal received by the CPU (MOS 6502) is taken from a higher frequency clock compatible with the TV color encoding system by the 6560/61 and divided to one close to 1MHz. For NTSC, that's 14.31818 MHz divided by 14 = 1.0227 MHz.

ie. is there a self-test of some sort that takes place at boot-up that would prevent the machine from booting to the BASIC interpreter?

Without a clock signal, the CPU can't do anything at all, not even a self test of the system. Yet there is in the kernal a series of routines that are performed by the CPU to check on things and that includes the determination of the amount of BASIC RAM.

Some help here Mike ?

I've ordered an FPGA development board to play around with generating VGA displays anyway. I'm just toying with the idea of being able to hook this up to the VIC data/address bus etc and doing my own display on VGA instead.

AFAIK, the VIC-I has been re-implemented in software only. However, the VIC-II has been fully re-implemented in hardware and one of the people who did a great job is Gideon Zweijtzer. Since the VIC-II is far more complex, I assume you'd want to chat with people like him about your idea.

[tlr]

Isn't nippur72 working on something like this?

The actual VIC-I logic should be fairly straight forward. Making it into an actual chip substitute requires some fiddling to get the I/O right with regards to timing + the analog video and to some extent audio stuff.

[groepaz]

AFAIK, the VIC-I has been re-implemented in software only.

na, there is an FPGA vic20 for the chameleon, and for the fpgaarcade board. i believe also for the mist. the vic-i is a lot easier to get right than the vic-ii afterall

but indeed, moving from a fpga implementation to an actual chip drop-in replacement is yet another story. it'd also not be viable for some years to come (the replacement will be considerably more expensive than an actual chip)

[SparkyNZ]

Thanks for the many replies guys. I've sort of parked this idea for a while while I'm playing around with a homebrew 6502 machine - which I'm thoroughly enjoying at the moment! But I'm keen to come back to it.

I do actually own a Turbo Chameleon along with my C64s so I'm familiar with what you were referring to.

I'd just like to get something working in the video department - on VGA rather than composite/SVideo so I'm not looking for a 6561 replacement. I just want to interface to the rest of the Vic and have a go at doing some Vic (video and sound) emulation myself for a bit of fun. I've fiddled around with the Vice emulator source in the past so I think I've got everything I'd need from a software point of view - for a starting point anyway. The key thing for me is just to get the Vic running without the 6561.. so maybe I need to start looking at how I can divide the clock frequency etc. Doing any sort of VGA controller is way down track for me at the moment.

Theoretically though.. I should be able to clock the system at a really slow rate so I can monitor the address and data lines shouldn't I? That way I'd be able to see write requests to the Vic, monitor the R/W pin etc?

The 6502 I have on my (other project) breadboard at the moment is clocked at about 2 clocks per second. Since I don't actually have a 6561 in the Vic motherboard at the moment I might have a go at feeding my clock into pin 35 where Vic would normally sit and see if I can get some activity.

[groepaz]

You'll have to check the datasheets of various ICs... eg iirc the 6502 can not run at arbitrary speed, it needs a minimum frequency to work right. the same might be true for other ICs. perhaps you want to get one of those cheap USB multichannel logic analyzers

[eslapion]

... moving from a fpga implementation to an actual chip drop-in replacement is yet another story.

Something like that...

it'd also not be viable for some years to come (the replacement will be considerably more expensive than an actual chip)

Sounds very much like something I said about a CIA replacement...

[eslapion]

...The key thing for me is just to get the Vic running without the 6561.. so maybe I need to start looking at how I can divide the clock frequency etc.

A simple 74ACT161 will do that for you.

In the 1541 drive, a 74LS193 and 74LS197 are used to divide the 16MHz clock down to 1MHz and 4 different rates for the encoder/decoder. No big deal there.

Top right corner of this image: http://personalpages.tds.net/~rcarlsen/ ... 1542-1.GIF

Theoretically though.. I should be able to clock the system at a really slow rate so I can monitor the address and data lines shouldn't I? That way I'd be able to see write requests to the Vic, monitor the R/W pin etc?

The 6502 I have on my (other project) breadboard at the moment is clocked at about 2 clocks per second. Since I don't actually have a 6561 in the Vic motherboard at the moment I might have a go at feeding my clock into pin 35 where Vic would normally sit and see if I can get some activity.

I have a modded VIC which can run at 1/16 the normal CPU speed without removing the VIC-I. This trick too uses a simple counter logic IC. Cascade 2 of them and you can run at 1/256 the normal speed.

I'd have to look it up for you.

[SparkyNZ]

I have a modded VIC which can run at 1/16 the normal CPU speed without removing the VIC-I. This trick too uses a simple counter logic IC. Cascade 2 of them and you can run at 1/256 the normal speed.

I'd have to look it up for you.

I've read that the older 6502's don't like running at slow speeds. I do have a few of the the modern ones so that shouldn't be a problem.

Do you think all of the other chips would be happy running ridiculously slow at something silly like 2Hz? Won't the Vic have old RAM chips that need constant refreshing etc? But... having said that.. I have already modded this Vic - it has 2x 8k RAM chips piggy backed on top of the BASIC and Kernel ROMs. Maybe it will be happy at the slow speed providing I use those and not the original onboard unexpanded RAM?

When I receive some more supplies I'm going to to make a couple of "snoop" cables to fit into the 6502 and 6561 sockets (allowing me to fit the 6502 into the top of the cable also). I'll be able to connect that up to my Arduino and do some sniffing. I'm really looking forward to that!

Thanks for the tips on the frequency division.

[tlr]

I've read that the older 6502's don't like running at slow speeds. I do have a few of the the modern ones so that shouldn't be a problem.

Do you think all of the other chips would be happy running ridiculously slow at something silly like 2Hz? Won't the Vic have old RAM chips that need constant refreshing etc? But... having said that.. I have already modded this Vic - it has 2x 8k RAM chips piggy backed on top of the BASIC and Kernel ROMs. Maybe it will be happy at the slow speed providing I use those and not the original onboard unexpanded RAM?

The keyword in the CPU datasheet is "fully static" which is true for the CMOS clones. I don't think any of the NMOS ones come in fully static. For the original 6502 the minimum frequency is 100KHz. The memory in the VIC-20 is SRAM so these will work at low frequencies.

[SparkyNZ]

The keyword in the CPU datasheet is "fully static" which is true for the CMOS clones. I don't think any of the NMOS ones come in fully static. For the original 6502 the minimum frequency is 100KHz. The memory in the VIC-20 is SRAM so these will work at low frequencies.

SRAM - awesome. I'll swap the 6502 for a newer one and give it a go. Just need the postie to hurry up with my components

On a slightly different note -is anybody here familiar with FGPA/CPLD devices? I'm just aware that FGPA/CPLD dev boards usually have the chip soldered directly onto the board (e.g. Altera Max II EPM240) Can you buy "programming" boards with sockets on them.. and preferably variants of these chips that aren't surface mount? Ultimately I'll be wanting the means of soldering a socket onto a prototype board that will take one of these chips, allowing me to pop one in and out as and when required.

[tlr]

On a slightly different note -is anybody here familiar with FGPA/CPLD devices? I'm just aware that FGPA/CPLD dev boards usually have the chip soldered directly onto the board (e.g. Altera Max II EPM240) Can you buy "programming" boards with sockets on them.. and preferably variants of these chips that aren't surface mount? Ultimately I'll be wanting the means of soldering a socket onto a prototype board that will take one of these chips, allowing me to pop one in and out as and when required.

I don't think there are any FPGA devices that aren't surface mount but perhaps somebody sells them mounted on a DIP adapter? Programming an CPLD/FPGA is usually done using JTAG* so a small pin header and a JTAG dongle is the only thing required to develop . This can easily be fitted directly on the adapter board. Note that this also allows programming them in-circuit.

* NOTE: FPGAs usually load up from an external PROM but this can also be fitted to the board and programmed using JTAG.

[SparkyNZ]

I don't think there are any FPGA devices that aren't surface mount but perhaps somebody sells them mounted on a DIP adapter? Programming an CPLD/FPGA is usually done using JTAG* so a small pin header and a JTAG dongle is the only thing required to develop . This can easily be fitted directly on the adapter board. Note that this also allows programming them in-circuit.

* NOTE: FPGAs usually load up from an external PROM but this can also be fitted to the board and programmed using JTAG.

Yeah, I'd be looking for something like this:
https://www2.hdl.co.jp/en/plcc68-series/ap68-01-m.html

That must be one of those adapter boards you refer to (which would be fine)... but of course then I'd need to get one containing my chip.. or would I? Having said that.. maybe I won't actually need an Altera Max II EPM240 chip?? I'm only assuming I'd need the same chip since that's what is on my development board. Perhaps I can find a different CPLD that will work just the same. I can't see me requiring 100 pins that's for sure. I have no idea if these CPLD's are created/programmed to a common standard or if it varies between manufacturer.

If all I'd need is a header to attache the JTAG USB dongle then that would be great. I haven't found a good "beginners" CPLD/FPGA forum yet. Need to find somewhere where I can ask all the wrong questions

[tlr]

Yeah, I'd be looking for something like this:
https://www2.hdl.co.jp/en/plcc68-series/ap68-01-m.html

That must be one of those adapter boards you refer to (which would be fine)... but of course then I'd need to get one containing my chip.. or would I? Having said that.. maybe I won't actually need an Altera Max II EPM240 chip?? I'm only assuming I'd need the same chip since that's what is on my development board. Perhaps I can find a different CPLD that will work just the same. I can't see me requiring 100 pins that's for sure. I have no idea if these CPLD's are created/programmed to a common standard or if it varies between manufacturer.

I was thinking more like this: https://www.xilinx.com/products/boards- ... lhae0.html
Google for "fpga dip board" or "breadboardable fpga module".

The various FPGA variants are highly incompatible between different series. Much more so than MCUs.