Ok, now that you have updated the schematic of V1.4 (now V1.5?) I have no more perplessity about its wellworking,
but I noticed that this patch is done with another gate located into a "single gate chip",
but all it can be done in a more elegant way with a single 74 chip.
I wrote a "pizzino" (see pic) with a possible solution, it's a theoretical schematic but it should work at first shot...
I hope this post will be welcomed.
This solution is based on double decoder '139,
with its A0 input the "Y" half selects which output (Dynamic or Static) will be driven by /CAS-TED signal,
so the switch will select the S-64k or D-16k ram bank.
The second half "X" is used as "LUT" and its /Q0 will be "L" only if the CLK are "L" during a Write cycle,
it will deselect the S-Ram lowering the ram input CS2 (that is active H).
So the "X" half will limit the CAS time to the falling edge of the CLOCK but only during a write cycle.
"Two things are infinite, the universe and human stupidity, and I am not yet completely sure about the universe." (Albert Einstein)