The schematic tool appears to have a few issues that are difficult to work around. As I mentioned in what I quoted above, I'm starting out with an approach that involves building a lot of the modules using the schematic tool, i.e. creating an Input file of type Schematic and then drawing the circuit out rather than writing Verilog for the module. When saving such a schematic, it automatically generates the Verilog.lance.ewing wrote:I haven't jumped completely into Verilog yet, although I'm mostly through reading a basic introductory book and have looked over a number of cheat sheets. I'm finding that using the schematic tool within Lattice Diamond to build a module is quite educational as well, since you can then easily see what Verilog it generates for the schematic that you've created.
The issue that has blocked me a number of times is that it seems to silently refuse to update certain changes to the Ports that are defined. For example, if I add a couple more ports to a schematic, the schematic to verilog tool runs automatically but the verilog output doesn't have the new (in this case) outputs. Likewise if I try to redefine the type of a Port, e.g. make it 8 bits instead of 1 bit, it seems to ignore this as well (or rather it logs an error saying that the port type doesn't match what it is connected to, which isn't true in this case). For a while I thought it was just something I was misunderstanding in using the schematic tool, e.g. perhaps in the way I was naming the nets, but when I create a completely new schematic and add the ports exactly as I was trying to modify the previous one to be like, it works. It seems that it is remembering something about the ports that were defined earlier when I saved it and then it won't update those if I try to change them. It's a bit of an issue because my plan had been to have the main top level module as a schematic block diagram like what I have shown above that I was building in Logisim. If I can't reliably update an existing schematic, it makes it quite difficult to continue building that schematic up over time, which could be many months. I've searched through the menus looking for some option to force a clean generation from the schematic in its new state but I can't find anything like that.
I know I can avoid all this by simply writing it in Verilog, but I was hoping to build up some schematics by hand, place the modules and components as I want them visually, mainly because a big part of the goal is to document things through schematic diagrams like I was doing previously in Logisim. Perhaps an FPGA tool is the wrong tool for that type of goal. I was hoping I'd get further on the simulation side using an FPGA tool though, i.e. to prove that the schematics I'd reversed are behaving as we'd expect.
My current work around for the above mentioned issue is to create a new schematic input file, then copy and paste the whole diagram from the broken one into the new schematic, save the new one and delete the old. Everything is fine with the new schematic then, even though visually it is identical to the one that was supposedly broken. Very strange.
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