Anyway to test cassette read signals?
Posted: Wed Jul 19, 2017 7:46 am
Does anyone have any utilities that allow testing of the read signal from a datasette? I had some utility programs for my C64 for azimuth adjustment, something like that would help if it ever existed for the VIC.
I'm trying to get a cassette interface to my FPGA based VIC20 working, but it won't read correctly from either a real C2N or from a Tapuino. I'm trying to work out where the problem may lie. Functionally what I am seeing is something similar to a C2N with a bad azimuth adjustment.
The only success I have had is with a very small basic program that loads correctly maybe 50% of the time.
I know my clock for the 6502 is a little off what it should be for a PAL VIC due to limitations of the PLL I have available, but I would have thought that would not cause an issue as the effect would be the same as with a C2N with a slightly different motor speed.
I'm also having to use a 5v to 3.3v logic level converter on the read signal, but checking with a scope that doesn't seem to be causing a problem. As I understand things the important edges on the read signal are negative going, which are nice a sharp both sides of the converter. The positive going edges seem generally OK too, there is a very slight ramp on them but again nothing I am overly concerned about.
As the signaling looks reasonable on the surface at least, that kind of points to a fault with the VIA. So I was thinking of trying to code something up that could read a sequence of pulses from a hand crafted TAP file played via my Tapuino to validate the operation of the VIA is correct, but I thought I would check if anyone had something like that already.
Alternatively if anyone can suggest a test for the VIA that mimics the operation of the ROM loader that would be good. My VHDL VIA implementation passes all of the VICE tests now, but that is not an exhaustive test and none of those really exercise edge triggered interrupts on CA1 which would be critical for the cassette interface.
Any thoughts or ideas are appreciated.
I'm trying to get a cassette interface to my FPGA based VIC20 working, but it won't read correctly from either a real C2N or from a Tapuino. I'm trying to work out where the problem may lie. Functionally what I am seeing is something similar to a C2N with a bad azimuth adjustment.
The only success I have had is with a very small basic program that loads correctly maybe 50% of the time.
I know my clock for the 6502 is a little off what it should be for a PAL VIC due to limitations of the PLL I have available, but I would have thought that would not cause an issue as the effect would be the same as with a C2N with a slightly different motor speed.
I'm also having to use a 5v to 3.3v logic level converter on the read signal, but checking with a scope that doesn't seem to be causing a problem. As I understand things the important edges on the read signal are negative going, which are nice a sharp both sides of the converter. The positive going edges seem generally OK too, there is a very slight ramp on them but again nothing I am overly concerned about.
As the signaling looks reasonable on the surface at least, that kind of points to a fault with the VIA. So I was thinking of trying to code something up that could read a sequence of pulses from a hand crafted TAP file played via my Tapuino to validate the operation of the VIA is correct, but I thought I would check if anyone had something like that already.
Alternatively if anyone can suggest a test for the VIA that mimics the operation of the ROM loader that would be good. My VHDL VIA implementation passes all of the VICE tests now, but that is not an exhaustive test and none of those really exercise edge triggered interrupts on CA1 which would be critical for the cassette interface.
Any thoughts or ideas are appreciated.
