Denial

Hello! It's been a REALLY long time since I've been able to post to this forum. Despite owning a VIC-20 for the last 10+ years, I've never really used them very much. But I've recently developed a strong interest in using them.

Anyway...

I'm toying with the idea of creating a custom add-on cartridge for some I/O stuff I want to do. Mostly audio at the moment. When looking at the pinouts here (https://www.c64-wiki.com/wiki/Expansion_port_VIC20), I see that I have two options: /I/O2 & /I/O3.

However, I've read that there are some popular carts that use those ranges for things like storing settings in EEPROM, for example.

So, my question is...what IO space would be "safe" in both of those ranges?

For example, where could I map 16 or 32 registers in the space $9800-$9BFF that would have the best possibility to avoid any address conflict with other carts?

Thanks for any suggestions.

The question should be: what other carts do you plan to use along with your custom cartridge ?

The Behr-Bonz uses the IO3 range for its control register and I know the Megacart uses these ranges. perhaps the new MIDI cart from Jim Brain uses them.

I honestly don't know of any legacy cart that uses these ranges.

Unfortunately there are carts out there that use one or both of /IO2 & 3. Many, instead of decoding a specific range of addresses within that region, just select on the line. So the only safe approach is to jumper between them, but that means the code that uses your cart needs to handle that.

It would be nice to have a list of carts and what I/O regions they use. For example the FE3 uses on $9C02 & 9C03.

my suggestion:
put a little 2 position switch for choosing between I/O2, I/O3 then this selection has to be inverted (a NOT gate, or equivalent) and the signal can feed the pin 3 (A=B in) of a 74LS85 (a 4 bit comparator): pin 6 (A=B out) will be the decoded line for your registers address (active H, invert it if necessary), with an undecoded area of 64 registers.
Feed the comparator '85 with bus address A9,8,7,6 and compare them with 4 pull-up resistors and 4 dip-switch.

Result:
your 64 registers can be moved in every area inside I/O2 and I/O3 space without manipulation of your wires or your PCB.
If at startup your software ask you the state of this 5 switchs you can move your registers in accordance with the external cartridge present at the moment!

Do it sounds good?

http://www.applelogic.org/files/74LS85.pdf

better:
use an inexpensive 8bit comparator 74LS682 and use as input:
0: I/O2
1: I/O3
2: A9
3: A8
4: A7
5: A6
6: A5
7: A4

74LS682 has internal pull-up: only dip switch have to be added to be compared,
remember that dip sw. 0,1 can't be open or closed both of them at the same time, or use a deviator to ground for comparing this 2 inputs.

The output is active Low (as the standard selection signal).

This decode a register area of 16 registers, if you need 32 registers: put the input "7" unconnected at both side of comparator.

Do it sounds better?

Sorry for the delay.

Those are some great responses. Thanks.

One thing I didn't mention is that I would like to eventually implement soft-switches in my designs. I like the idea of setting the positions in software, burning to an EEPROM, etc. So I have some more research ahead...

I also wished we had an official list of I/O locations used by any legacy (if any) and modern carts.

Ok,
try to follow my idea......
Target: a way to permit at software to set the bank address of the cartridge.
Immagine:periferics or memory expansion (RAM/ROM) use every decoded lines (I/O2, I/O3, /BLKs, /RAMs...)
My solution:
take a serial in parallel out (SIPO) schift register that has this input:
A) CLEAR: wire it with /BLK5 (or BLK3 if your SW is on BLK5) ANDed with /RESET line
B) DATA IN: wire it with DATA bus 0 (or 1,.....7)
C) CLOCK: wire it with /BLK2
D) serial output at end of register (carry): wire it with a CLK input of a D registers that has to store the bank address

With a routine you can fill the SIPO starting the word with "1",
if SIPO is 8bit you have to put "1" followed by 8bit that have to be stored as address bank,
the first "1" will carry out from SIPO, and it will store the data from SIPO to D register

MCes wrote:Ok,
try to follow my idea......
Target: a way to permit at software to set the bank address of the cartridge.
Immagine:periferics or memory expansion (RAM/ROM) use every decoded lines (I/O2, I/O3, /BLKs, /RAMs...)
My solution:
take a serial in parallel out (SIPO) schift register that has this input:
A) CLEAR: wire it with /BLK5 (or BLK3 if your SW is on BLK5) ANDed with /RESET line
B) DATA IN: wire it with DATA bus 0 (or 1,.....7)
C) CLOCK: wire it with /BLK2
D) serial output at end of register (carry): wire it with a CLK input of a D registers that has to store the bank address

With a routine you can fill the SIPO starting the word with "1",
if SIPO is 8bit you have to put "1" followed by 8bit that have to be stored as address bank,
the first "1" will carry out from SIPO, and it will store the data from SIPO to D register

I think I have a rough idea of what you're describing. I will have to draw it out on paper to really understand.
I'd be really interested in following any hardware projects you've done for the VIC-20. Do you have a blog or something?

Thanks!

Thanks for your words...
No, I haven't a blog but you can find on this forum some ideas of mine.

It's only a theoretical circuit, but it could near to be working:
Q6 out of registered SIPO and it's negation (/Q6: Q6 via NOT gate) will generate the 2-bits for comparing with IO2 and IO3 lines (only 1 line will be "0" at time).

UN-registered Q7 SIPO out (Q7S) will CLOCK the (SIPO)REGISTER,
Q7 out bit of registered SIPO will lock the SIPO CLK to prevent corruption of serial data during the normal activity of bus, only an HW reset will unlock the game!

So SIPO has to be feed with "1" followed by I/Obit and 6 bits (the A9...A4 registers area address).
I/Obit means: 0 for map it on I/O2 area, 1 for map it on I/O3 area

I think that this solution use a minimum number of chip,
may be that using some 6522 (or 6520 or else) in place of HC541 and HC273 will be possible to use less chips for final decoding (HC154), but I prefer simple registers.
The diagram will become very simple if you can put all inside a CPLD (all, or all less the in/out register HC541 HC273 for saving a lot of CPLD pins)

If you are still searching for another option, I have one that I use. I wired in another decoder, like a 74LS139, and used IO0 to select this decoder. This is the IO space used for the VIA's. This will break up this IO section into four pieces: $9000, $9100, $9200, $9300. This opens up address ranges from $9200-$92FF, and $9300-$93FF, and doesn't interfere with anything. It works great.