WIP(?): A proposal for a VIC-20 with 60K RAM

[Mike]

... with the following approach:

Code: Select all

 /BLK6  VR/W  /LORAM | /CSROM6 /CSRAM6
---------------------+-----------------
   0      0      X   |    1       0
   0      1      0   |    1       0
   0      1      1   |    0       1
   1      X      X   |    1       1

Code: Select all

 /BLK7  VR/W  /HIRAM | /CSROM7 /CSRAM7
---------------------+-----------------
   0      0      X   |    1       0
   0      1      0   |    1       0
   0      1      1   |    0       1
   1      X      X   |    1       1

Code: Select all

 VA12+VA13   SPhi2     VR/W    /VICRAM   /CPURAM   |   /CSROM    /CSRAM
---------------------------------------------------+--------------------
     0         0         0         X         X     |      1         1   (should never occur...)
     0         0         1         0         X     |      1         0
     0         0         1         1         X     |      0         1
     0         1         0         X         X     |      1         0
     0         1         1         X         0     |      1         0
     0         1         1         X         1     |      0         1
     1         X         X         X         X     |      1         1

Right, some explanations:

- These equations allow for RAM "under" Character, BASIC and KERNAL ROM,
- four register bits (/LORAM, /HIRAM, /VICRAM, /CPURAM) define the mapping,
- write accesses of the CPU always access the corresponding RAM,
- VA12+VA13 is the effective /CS of the Character ROM.
- Character ROM access is differentiated between VIC and CPU, either one can access RAM or ROM.

... just the result of 1/2 h deep thought.

... if I/O 2 and I/O 3 are filled, those are 62 K RAM.

[eslapion]

@Mike
Obviously since your project is well structured, coherent and more than likely perfectly feasible, we're bound to see kakemoms exhibit strictly no interest in it...

I suggested the multiplexed address lines and fake address solution as a favor to him. I have absolutely no interest in a project like that.

Personally, if I wanted multiple kernals, I would simply use a 27C256 with a 3 position switch on a 2364 pinout adapter, exactly like I did dozens of times for the C64.

[Kakemoms]

@Mike
Obviously since your project is well structured, coherent and more than likely perfectly feasible, we're bound to see kakemoms exhibit strictly no interest in it...

I suggested the multiplexed address lines and fake address solution as a favor to him. I have absolutely no interest in a project like that.

Personally, if I wanted multiple kernals, I would simply use a 27C256 with a 3 position switch on a 2364 pinout adapter, exactly like I did dozens of times for the C64.

Eslapion,

First you cut in months old comments from Mike and suggest they all apply to your current discussion. Now you try to speak on my behalf without even knowing me or having spoken with me ever. I suggest you keep to the subject without trying to make some kind of drama out of every post each time your idea is not something that fits a discussion or can add positively to it.

Mike,

I think your ideas are very interesting. I haven´t had the time to get a good grip of the setup here, but I hope you continue to think on it and explain it further as it develops. After my holidays I hope to get some more time for experimental work instead of having to bring up noisy kids.

[eslapion]

@Kakemoms
I think you're frustrated because I'm not the only one who thinks some of the stuff you post is technical nonsense. Also, you just shoved aside a solution I proposed that did exactly what you wanted without a risk of damage to the VIC-20 in which it could be implemented.