FPGA replacement for VIC I chip?

[lance.ewing]

Unfortunately it is working out the logic gates that I'm struggling with. I did spend quite some time trying to work out the logic diagram for a cell in one of the control registers. Some parts of the end result didn't seem to make much sense to me, so I was sure I'd confused recognition of some parts of it, e.g. not quite seeing where the diffusion ended, or where something made a connection between layers. It's within the logic gates that things get a bit crowded and overlapping and difficult to see. In the end I decided that at this point I didn't really need to know things at that level. I already knew it was a 1 bit cell in a control register, and based on the lines going in to and out of it, I could make educated guesses about what was happening inside. I do want to revisit it at some point, but its logic gates that are the real time waster. Without having photos of each layer, its hard to be certain of where certain edges are.

It was a similar approach with the shift register. I could see that data was coming in to it in parallel from the main 8 data lines, and those links between each 1 bit cell controlled by pass transistors look suspiciously like the mechanism for shifting the value along the bit positions. From Segher's partially labelled die shot, I could see that the colors were very close to this register, and so it all seemed to tie together.

For reference as to what part of the die shot the shift register lives in, take a look at this attempt to label some of the functional areas:

https://sites.google.com/site/mos6561vi ... ks_wip.png

The box labelled "CHAR DATA" is where the 8 bits of character data come in from the data lines. The metal lines leading down from that box towards the shift register are then linked to a number of pink poly and green diffusion lines that carry that character data in to the shift register in parallel. There must be a pass transistor somewhere that controls when that data is loaded via that path.

We can also see from CR F and CR E that there are poly and diffusions lines on the left hand side of those control registers that are linking those down to the boxes I've labelled as BRD, BCK and AUX. The CHAR COLOR and MODE boxes are linked by lines back to D8-D11.

For the box labelled "ADDRESS COMPUTATION", that is once again an educated guess based on what is going in to and coming out of it. I can see the start addresses for the screen matrix and character memory going in to that block. I can also see lines coming up from the bottom of the die shot that are presumably the counter values it needs for calculating the address. The box marked CELL INDEX is a guess based on the fact that this is coming from the data lines and that the address computation logic needs this. The biggest clue though is that the address lines themselves go in to and out of this section. Segher has labelled some of the lines in this area with the prefix "bm" followed by a number. I'm not yet sure what the letters "bm" stands for though. Any ideas?

The box labelled "TONE GENERATORS" is another fairly safe guess I think based on the fact that there are four of them and they lie directly between the tone control registers and the SND output pin. I can also see the CR E volume value linking through to this area.

I haven't labelled it, but I think the control registers for the POT values are to the right of the tone generator area.

Somewhere down in the unlabelled area in the bottom left must be the vertical counter. I can see links coming from there up to the memory mapped raster line register(s).

[lance.ewing]

After staring at one of the cells in the shift register for a bit, this one actually looks like it might be a lot easier to spot the edges of the polysilicon and diffusion areas. I haven't yet started to draw this out on a piece of paper to work out the circuit, but here is a labelled step towards that, showing all the various transistors within one cell, and the connections coming in to it:

We should be able to work out the circuit now. A combination of depletion mode transistor and enhancement mode transistor is an inverter. A couple of those cross coupled (haven't yet checked to see if these are) is usually how these register cells store a high or low value.

The pass transistor connected to the metal line on the left is the one controlling the parallel loading of the character data in to the register cells.

The pass transistor connected to the metal line on the right is the one controlling the shifting of the bits along the cells (haven't yet worked out what direction it is going).

Not yet sure what the pass transistor connected to the second metal line from the left is controlling. Should become apparent once we start to draw out the circuit.

It occurs to me that we can pretty much guess what these metal lines are by working out what they control, i.e. we don't necessarily have to track them back to their source.

Lot's of educated guess work, but for a project so big, I think this seems the best way to keep our sanity.

[lance.ewing]

I think I might have picked the wrong metal line as the shift control line. The second metal line from the left is looking more likely, since it appears to pass through a signal to the same line through which the parallel load happens. That makes a lot of sense if you think about it. A cell in the shift register either loads from the parallel input or from the cell next to it. Staring at it a bit more just now, I'm nearly 99% certain it's the second metal line. There is no other connection between each cell, so that pass transistor has to be the one that shifts the value to the next bit position.

Check out this tutorial: http://wiki.nesdev.com/w/index.php/Visu ... _registers

If a similar shift register design was used in the VIC as shown in that tutorial, then the metal line on the far right might be what the tutorial calls the Invert control signal.

I might need to go back and modify some of my earlier posts, so as not to put people on the wrong track. That white circle in the first image is more than likely in the wrong place

Edit: (does a quick read up on shift register theory in Mead & Conway's "Introduction to VLSI Systems" book...) So it might be that both the second metal line from the left and the metal line on the far right control the shift process. I think what we must have is a dot clock signal that is, as we know, 4 times the machine cycle. Phase 1 of that dot clock signal is probably on one of those lines and phase 2 of the dot clock signal on the other. In the Mead/Conway book, it shows "level restoring inverters coupled by pass transistors". Each bit therefore has two inverters. Within the cycle of the dot clock, a cell's level gets inverted on entry in to the cell, then inverted half way through the dot clock cycle, and then that signal passes through to the next cell at the start of the next cycle of the dot clock. So I think both signals control the shift, but if we use the terminology shown in that Visual circuit tutorial I linked to above, then strictly speaking the second metal line from the level is the "Shift" one that controls the value passing in to the next cell, and the metal line on the right is the "Invert" one that inverts the level halfway through.

[lance.ewing]

Hope people don't mind too much with how verbose I've been in trying to work this out. I figure that people will be interested in seeing how I'm tackling the problem, spotting mistakes, winding it back, trying again, eventually getting somewhere.

Anyway, I may have finally worked out the logic gates being used. I started by drawing lines around the polysilicon (red) and diffusion (green) areas like this:

At first it seemed like there were twice as many depletion mode and enhancement mode transistors as I was expecting. I was expecting to see two inverters per 1-bit cell, which would normally be one depletion mode transistor and one enhancement mode transistor each. But instead in the above image there are four depletion mode transistors and four enhancement mode transistors in the 1 bit cell (I'm not including the pass transistors in the enhancement mode count).

One part of the image above that confused me a bit was in how the depletion mode transistors were connected. It's probably the one bit that is difficult to spot the edges of, but my best guess is what is shown in the diagram above, i.e. every two depletion mode transistors have their gates connected to each other. The more I thought about it though, the more this seemed right, since the this is also happening with the enhancement mode transistors. Every two of those also have their gates connected. What is difficult to spot though is whether both of those depletion mode transistors have their gate connected to their source. The smaller one doesn't appear to. The bigger one does appear to.

I did a bit of research and this configuration (where the two depletion mode transistors have their gates connected, the two enhancement mode transistors also have their gates connected, and only the first of the two depletion mode transistors has its gate connected to its source) is known as an inverting super buffer:

nmos_inverting_super_buffer.png (5.18 KiB) Viewed 1792 times

Edit: Adding a labelled version below of a single inverting super buffer from the shift register to show how it relates to the diagram above:

So rather than each 1-bit cell in the shift register containing two inverters, they instead contain two inverting super buffers; at least that is what I assume them to be. They're connected up in the same way as in the inverting super buffer diagram shown above. The logical behaviour of a inverting super buffer is the same as an inverter though. Super buffers are used to reduce the propagation delay time, when driving large capacitive loads, over what is seen when using only a single inverter. Lot's of words in that last sentence that I'm still getting my head around, but the main point is that logically its an inverter; they're just making it faster.

I will be posting more on this later today. I'll show how the pass transistors and multiple 1-bit cells are joined together. And then I'll finally get to the point of overlaying that circuit on top of the die shot image.

[srowe]

Hope people don't mind too much with how verbose I've been in trying to work this out.

I find it fascinating that you can reverse-engineer so much from a picture, keep going!

[joshuadenmark]

Following too, very interesting. Always glad to learn something new from experts (and for free) thanks!

[lance.ewing]

The following diagram shows the complete circuit for a single 1 bit cell in the shift register:

shift_register_1_bit_cell_circuit.png (13.62 KiB) Viewed 1759 times

Some points to note about this:

• The input to the top inverting super buffer is either the parallel input (controlled by the P1 pass transistor) or the output of the 1-bit cell above it (shown in the diagram as the SHIFT line coming from above.
• The bottom inverting super buffer is the same as the top but rotated 180 degrees. I've deliberately left the Q1, Q2, Q3, Q4, Vin and Vout upside down to show that it is a rotated version of the one above it.
• The output of the top inverting super buffer becomes the input to the bottom inverting super buffer, but only when the P3 pass transistor lets it through. Note that the INVERT label isn't meant to say that the pass transistor inverts the value, but rather that the pass transistor lets the value through to the second inverting super buffer. It's probably not the best name for that line. It's essentially the opposite phase of the SHIFT line. They would be the two phases of the same two-phase non-overlapping clock signal, the rate of which would be 4 times the normal machine cycle (not sure what happens to these signals when the VIC chip is not currently within the video matrix though, since obviously the character data isn't playing a part in the border area).
• The output of the bottom inverting super buffer becomes the input to the next 1 bit cell in the shift register, but only when the P2 pass transistor lets it through.
• The point above answers the question about what direction the shift is happening. It's going down, which makes sense if we track the parallel input lines back to the data lines. The D0 line enters the top 1-bit cell of the shift register and will be the last bit to come out of the shift register.
• The above diagram would be the case for the bits from position 1-6, but not for bits 0 and 7. Those are at the two ends, so may have some slight differences from the bits in the middle. A quick glance at each does suggest this. The top one doesn't have the parallel load pass transistor. D0 just goes straight in. And you know what? There isn't an 8th cell! There are only seven. I think we'll need to look at D0 and D7 coming in separately. It appears that D7 passes straight through, to wherever the output of the shift register goes, as soon as the parallel load pass transistor lets it through. It isn't stored in the shift register. I guess this makes sense when you think about it. It's needed straight away.

If we think of the inverting super buffer as simply a logical NOT (ignoring for the moment the probably important reason that they chose to use a super buffer for the inverter), then the diagram can be simplified, using a mixed notation, to the following:

shift_register_1_bit_cell_inverters.png (5.53 KiB) Viewed 1759 times

[lance.ewing]

This one shows the seven 1-bit cells joined together, and the 8 character data lines coming in. It also shows that CD7 goes straight out through the bottom output, and that CD0 goes straight in to the first cell. This placement is roughly where each part appears within the die shot.

Will be interesting to see where that output line at the bottom leads, but that might have to wait until next weekend unfortunately.

Edit: In case it isn't obvious, all the P1 pass transistors are connected to the same metal line, all the P2 pass transistors to another metal line, and all the P3 pass transistors to a third metal line. This can be seen in the die shot, but I haven't shown them being connected in the diagram above.

[eslapion]

I hadn't thought of it at the transistor level and what you describe doesn't correspond to what I was told about NMOS technology.

IIRC, transistors are used to pull down in NMOS and resistors are used to pull up.

I think the best person to help you interpreting what you see on the 6561 die shot is Thomas 'Skoe' Giesel, the designer of Easy Flash and Easy Flash 3.

He did this level of interpretation for the PLAs of the C64.

[lance.ewing]

Thanks for the tip regarding Thomas 'Skoe' Giesel. I'll try to track him down and see if he can comment on the above.

My analysis is based mainly on what I've read from the following book:

http://ai.eecs.umich.edu/people/conway/ ... IText.html

Page 5 of the following chapter 1 PDF talks about the reason for the lack of resistors.

http://ai.eecs.umich.edu/people/conway/ ... Ch1-1s.pdf

I'll repeat what it says here for convenience:

"Were there an efficient way to implement resistors in the MOS technology, we could build a basic digital inverter circuit using the configuration of figure 2a." It then gets in to the lower level details a bit, but ends that paragraph by saying: "Implementing a sufficiently large inverter pull up using resistive lines would require a very large area compared to that occupied by the transistor itself."

"To circumvent this problem, a depletion mode MOSFET is used as a pullup for the basic inverter circuit, symbolized and configured as shown in figure 2b."

These are the diagrams that the text is referring to:

I've included figure 2c as well, which is one where they show how it is fabricated at the silicon level. Depletion mode transistors are recognised by their size. They're usually much larger than the normal enhancement mode transistors, such as the one used in the pull down part of figure C. All that is is a poly line crossing a diffusion area. It doesn't get any bigger as it crosses the diffusion area. Figure 2c also points out that the large poly area used in the pull up is connected to the diffusion part at the bottom. This is the source of the top transistor. Depletion mode transistors when used as a pull up will have their gate connected to their source.

In the complete shift register circuit diagram I showed, wherever there is a depletion mode transistor, it could be replaced with a resistor. It serves the same function, which is as the pull up. Each inverter therefore has both a pull up transistor and a pull down transistor. People seem to use different symbols to represent the depletion mode transistor. The one I used was a copy and paste of an image I found on the net when searching for "nmos inverting super buffer". We can see from the picture above that Mead and Conway used a slightly different symbol, and I've seen other people make it more obvious what the depletion mode transistor is doing by including a resistor like symbol above it.

[Kakemoms]

Thanks for the tip regarding Thomas 'Skoe' Giesel. I'll try to track him down and see if he can comment on the above.

My analysis is based mainly on what I've read from the following book:

http://ai.eecs.umich.edu/people/conway/ ... IText.html

Nice book! I never looked much into NMOS technology and its a joy for the eye to see the simplicity of a NAND.

Great work by the way! Tracing all those diffusion zones and poly lines makes it a lot easier to understand.

By the way; have you looked into the DAC yet?

[lance.ewing]

For the most part, even I can understand that book. Where it starts talking about equations and showing graphs, my mind starts switching off, but I figure that those lower level discussions are more relevant to the design process. What we have when attempting to reverse the circuit is an already designed chip. So I'm looking mainly for information in the book that can aid in recognising the components and the logic they form a part of. And yeah, those diagrams of the logic gates at the silicon level are so simple its very easy to see how they work. Obviously its not always laid out as shown in those diagrams though. Once you work out where the depletion mode pull up is, and where VDD is, then it's a matter of seeing what poly lines you have crossing the diffusion line(s) that leads from the source of the depletion mode pull up to VSS. If it's an inverter, there'll be only one enhancement mode pull down. If there are two in series, it's a NAND, and if there are two in parallel, its a NOR.

No, I haven't looked at the DAC yet. I've mainly been looking at where all the various data, address, and control lines are going.

[eslapion]

@lance.ewing
In an exchange about this subject last year, Skoe said this:

The NMOS chips can drive a load of 100 µA (!) with VOH min = 2.4 V (look at http://archive.6502.org/datasheets/mos_ ... v_1982.pdf page 3). And it takes ages to get to the final voltage of about 3.7 V, because the high side FET is an N-channel device (look at PLA dissected, page 22, diagrams from 7700/8700 PLA - with practically no load).

The document called PLA dissected is here:
http://www.zimmers.net/anonftp/pub/cbm/ ... sected.pdf

I can understand a couple of things now looking at this and trying to get an intuitive understanding of how these work:
* This is always a small amount cross conduction even when no switching occurs - energy inneficient design...
* Switching the output from high to low causes a lot of cross conduction since both FETs conduct for a brief period of time
* Switching the output from low to high is pretty slow since the gate of the depletion mode FET recharges itself with its own leakage current.

[Kakemoms]

For the most part, even I can understand that book. Where it starts talking about equations and showing graphs, my mind starts switching off, but I figure that those lower level discussions are more relevant to the design process. What we have when attempting to reverse the circuit is an already designed chip. So I'm looking mainly for information in the book that can aid in recognising the components and the logic they form a part of. And yeah, those diagrams of the logic gates at the silicon level are so simple its very easy to see how they work. Obviously its not always laid out as shown in those diagrams though. Once you work out where the depletion mode pull up is, and where VDD is, then it's a matter of seeing what poly lines you have crossing the diffusion line(s) that leads from the source of the depletion mode pull up to VSS. If it's an inverter, there'll be only one enhancement mode pull down. If there are two in series, it's a NAND, and if there are two in parallel, its a NOR.

No, I haven't looked at the DAC yet. I've mainly been looking at where all the various data, address, and control lines are going.

Hehe.. well it took me some years to get those into my head as well, so don't bother unless you are designing completely new basic elements. The physics behind (and matematics) predates the transistor with some decades, and with digital systems everything becomes neat 1's and 0's so we don't have to bother with the statistics of quantum theory.

Now, the first equation (in book 1) is actually becoming more important these days as everybody are looking into high-mobility materials (which is my field). Silicon has a pretty lousy mobility which tends to limit the speed and low-power devices we have today.

With the layout I think you have nailed it down. Just for the fun of it I tried to map out the polysilicon myself and the result matched yours. You can even see the contours a couple of places that might be from the ion implant step, so the guy taking his time with the microscope did an excellent job.

[eslapion]

@lance.ewing
The super buffer you describe appears identical to those found in the CSG PLA and described on pages 32-34 of PLA dissected.