Hi - new here and have a quick question for you...
Just acquired a nice clean VIC and upon opening her up found this wired modification to the board:
Anyone know what's going on here?
The box and case have matching serial no.s (GWB 70647) but the board has a sticker showing '14622' - so I'm guessing the board and case have been swapped over at some point??
Thanks for any info.
I should also say that the machine seems to work perfectly.
This looks to me like an attempt to replicate the Phi1 clock distribution logic, which normally is only present in the DIN variant, on the 2-prong VIC-20.
That logic is formed by UC2 and UC3 and takes input from UB4 pin 11 (which is driven by PPhi1 of the VIC chip) and pin 3 of the 6502 (Phi1, normally unconnected in the 2-prong variant), and ultimately generates a new VR/W signal, which then is wired to pin 10 of UD2.
The original VR/W signal should have been disabled. Is the trace coming from pin 11 (top right corner on first photo) of UE8 cut somewhere? (Edit: indeed it is, I see the pin has been clipped!)
It generates a slightly better defined VR/W signal than before the mod.
On the 2-prong, the VR/W signal is simply disconnected from CR/W during VIC fetches, but it is not actively driven to H-level (i.e., read) as in the DIN variant. Many RAM expansions are connected to VR/W though, and not CR/W. I can imagine this might corrupt memory in an external 3K expansion under the following (ultra rare) condition:
- RAM has been written in the range $0400 to $0FFF, and in the following half cycle VIC also tries to fetch from that range.
- The cartridge is still connected to the CPU data and address bus, as UD8, UE8 and UF8 separate the CPU and VIC bus during VIC fetches.
- The VIC fetch also activates one of the /RAMx signals, and the external RAM expansion picks up whatever is present on the data and address bus of the CPU,
- which needs not necessarily be the same data that has been written in the half cycle before. Now that VR/W has a prolonged transition time from write to read, errorneous data may be written to the external RAM.
Normally this condition doesn't ever happen in normal operation, as there's no good reason to point the VIC chip to the address range $0400 to $0FFF for screen or character data. On an unmodified VIC-20, the external RAM cannot be accessed by VIC due to the bus separation mentioned before.
