eslapion,
While writing an article about the C64 PLA I stumbled over your article here. It's a very good, systematic work. I also checked several PLAs and replacements and came to the same result as you: The M27C512-90B6 is better than its reputation. It works on most C64 boards with several extensions tested and I also didn't find any unusual glitches. I also checked it with my external KERNAL cartridge, which has certain timing requirements. It worked without problems.
Note: This is not the result for any random PROM PLA replacement, but for this very type only. We found lots of C64s out there which failed at this or that and it turned out that they had a bad PROM PLA replacement. I think these experiences made some people (including me) very skeptical. You also mentioned that it depends on various properties of the PLA if it works well or not.
The result of your article are clearly explained and I can confirm most of it. Please don't take it personal that I have some remarks about a few mistakes and questions:
As said earlier, the Commodore made PLA is a clone of something that existed before. It is simply improved over the original and is about twice faster
Twice faster? Did you measure the actual values? Or do you mean the rating? Do you know a rating for the CSG parts?
You make all your measurements with a threshold voltage of 2V. Actually it's about 1.3V for the NMOS chips used in the C64. However, it makes no big difference. All measurements I did used a threshold voltage of 1.5V and came to similar results as yours.
Excuse my naivety but aren’t the half cycles of the CPU and VIC-II supposed to last about 500ns each?
Yes, they are. But you forgot that in these cycles a lot of work has to be done. The addresses are not set up right at the beginning of the cycle. It gets worse because of the bus multiplexing in the C64. But I think you realized this already.
There are negative stutters on cycles where the kernal ROM is accessed and positive ones on cycles where the 6510 is turned off
Same explanation here. Unfortunately you don't have Phi2 on your captures, but I guess that these spikes are at the very moment when the bus control changes from CPU to VIC and vice versa. In that time some address lines are floating and pulled up slowly by resistors only, leading to intermediate states which are also decoded by the PLA.
NMOS technology, which uses transistors to drive a signal from 5V to 0V but uses a resistor to drive a signal from 0Vto 5V. This means every time the PLA is sending a 0V signal, it does so by shorting a resistor between the ground line and the 5V line, effectively turning it into a small heating element.
Well, this is half-true for internal logic. There we don't have resistors but depletion mode FETs, which have a similar but not identical function. And by the way this is even not the case for all internal logic, but for most of it.
This also means a signal transition from 0 to 5V will take much more time than a transition from 5V to 0.
This is also not generally true (despite the fact that it never rises to 5V
). An NMOS inverter (and also other gates) can be tuned by many means: The ratio between pull-up FET and pull-down FET can be changed, this changes the inverter voltage and also t_up and t_down. Super buffers can be used when both edges must become steep. And bootstrap circuits can be used to push a gate voltage above VDD, which speeds up the low => high edge significantly.
Probably you refer to an NMOS output here: For this it's even less true: An NMOS pad driver uses a normal Totem Pole driver with huge FETs. But as they don't have a bootstrap circuit usually, you get the effect you mean: The closer the output voltage comes to VDD - Vth, the less drive (I_ds) the pull-up FET (N-Channel!) has. When the output voltage is low (e.g. lower than 2 V) the driver has a similar strength then in the other direction. Only when the voltage is above 2 or 3 V the current is much lower, leading to a very slow rise time at the end. The final output level is about 5V - 1.3V, because there the current goes towards 0.
This means that the ramp time 5V => 1.3V is roughly the same as 0V => 1.3V for output drivers. Roughly means something like +/- 5 ns, which plays no role at all considering cycle times in the ball park 500 ns.
These effects can also be seen on your captures.
Clearly this is something caused by the signals fed into the PLA and not the PLA itself.
Indeed.
unless you combine a very fast kernal with the slow original CG
That's true. Don't forget cartridges which my use very fast CPLDs and CMOS RAMs etc. That's one of the resons I added these 100 Ohm resistors in the data lines of my cartridge designs: To reduce current peaks because of these effects.
After all, the M27C512-90B6 is rated for a response speed of 90ns.
> Perhaps adding a capacitor on the CASRAM output of these chips to increase the transition time could do the job of delaying the signal.
This may be needed on some boards, yes. My own M27C512-90B6 has an actual propagation delay of about 20 ns, it refuses to work with my KU board, probably because of the lower propagation delay compared to other PLAs.
Note, if you add a capacitor there, you should do it on all outputs. Otherwise you create the chip select overlap
Well, CBM made this with their CASRAM RC delay already :/
Sure enough, when measuring the 5Vdc load on the PSU, it shows a healthy 1.25A when using the MOS 906114-01. It rises to 1.32A with the 82S100. However, the M27C512-90B6 turns the 64 into a lean machine at only 1.12A.
Oh, that's an interesting experiment! I'll do the same with my machine. Thank you for the inspiration