How to read bits from tape

[nippur72]

does anybody knows how to read the state of the "data" bit from the tape interface? I haven't found it explained in the reference guide nor in the other docs I have. I understand the VIA chip has to be programmed but don't know how.

I need to play with tape signals and I want to write a sort of oscilloscope. I was thinking of changing border color according to state of this data bit, so that the height of the stripes on the border give me an idea of what there is on tape.

[Mike]

The cassette read line is connected to CA1 in the VIA #2.

This is bit 0 in the address $912C (decimal 37164).

So this code should work:

Code: Select all

loop LDA $912C
     STA $900F
     JMP loop

... but doesn't within VICE. (I checked with a TAP file) Could someone test this on a real VIC?

Michael

[nippur72]

is it $911C perhaps? Anyway it doesn't work on real Vic neither. I think the VIA has to be programmed someway before the data bit can be read (more or less like keyboard or joystick reading).

[carlsson]

From what I understand (after disassembling ROM), $912C is a control register you write to, to enable signals such as the read line. The data arrives some place else. I used my memory map and tried to follow the ROM, but I didn't find exactly where things happen when you load a file. Actually, I believe you should have a look somewhere into zeropage $90-$C0, at least the Kernel routines seem to work that way.

[nippur72]

There is a good program on the funet archive called "Tape Ton", which read the cassette data bit and plays it back thru the volume register, resulting in a sort of audible playback.

After deassembling it I discovered you have first to enable the cassette line via the VIA register $912C and then wait for an interrupt, checking the bit n.2 of $912D. I have not yed understood if the interrupt is flagged on the bit change or on the "rise" time.

Here is the monitor code that I wrote, but for monitoring purposes, "Tape Ton" is better (because you don't have to look at the screen).

Code: Select all

main:
   lda #$FC
   sta $911C   ; enable cassette motor

loop
   lda #$01
   eor $912C   ; bit 0 cassette read line
   sta $912C

loop_1:	
   lda #$02
   bit $912D   ; check for interrupt flag, cassette line
   bne loop_1
   lda #1
   eor 36879
   sta 36879
   jmp loop

Another interesting thing is running Tape Ton WITHOUT the tape plug connected, in which case the VIC20 is turned into an RF detector: the tape interface circuity works as an antenna, grabbing the nearby EM field. The result is that sound change as you approach the Vic or if you caress it on its back

[carlsson]

Aw, how suitable for the Friendly Computer to react when you caress it.

[mercifier]

As far as I know, the VIA chip can be programmed to trig interrupts on either raising or falling edges on the CA/CB pins. I think the normal tape transfer uses only one of them, but maybe it would be possible to toggle from raising to falling after detecting a rasing edge, and the other way round. This way you could read the tape as if it was a 1-bit sample.

[nippur72]

13 years later and I still don't know how to read the cassette bit correctly

On the C64 it seems to be a lot simpler: it's bit 4 on $dc0d. You wait for high, then wait for low, and the pulse is complete.

But on the VIC20 it works differently... very strange... I supposed they were identical.

Has anyone managed to sort it out?

[srowe]

Has anyone managed to sort it out?

It's the one bit of the KERNAL that I've not really got to grips with. As far as I can see the dipole mechanism is identical to the PET, C64 etc. all that's different is how that is realized, 6520 vs 6522 vs 6526.

[Forbidden64]

According to the programmer's reference guide, unlike most of the other commodores, the VIC-20 6522 VIA chip actually works! This would mean that the bits are transparent to the user. The way it is supposed to work in most cases is that the VIA chip grabs all the bits one at a time and shifts them until it gets a byte, then latches the byte. When it is ready then you can retrieve your byte. I'm no expert or anything but on every serial to parallel chip i have ever seen, that is how it is supposed to work. My understanding is that it didn't work on the 6526, so they did the serial to parallel operation in software. That said, why not use the byte in conjuction with the jiffy clock and then you can derive what the length was, backward. That is, get the byte, and map the LSB to MSB from a loop representing what the bits were, and since we know what the clock lengths are, you can see what it would look like on a scope.

Now that gets me thinking of a post from a while back...the datasette is pulled high all the time on the CIA by a 3.3K resistor tied to the 5V rail. Then when the datasette pulls it low, 5V goes to an open drain back on the datasette through a logic chip to ground which pulls that particular wire low. Is there a way you could tie that line after the 3.3K resistor, and before the pin going into the VIA over to the user port to do what you wanted to do? I see no reason why not...I'll edit this comment when I find the appropriate pin, and resistor number.

There was a guy in Italy who did an exhaustive amount of research on datasette...I am boggling my mind trying to remember his name!!!
He even dissected all the turbo tapes etc. and had scope stuff on his page. That is where I found that Rabbit turbo tape was 140 baud for example if memory serves(it doesn't seem to). I'll hunt around and update this if I can find him.

[Forbidden64]

Ehem, well While what I wrote is out of the reference guide, what it didn't tell us off the bat was that there was a way to do this without a soldering iron. Address 911d has something to do with it, and a section of a register called CB2? I have to admit it is freakin greek to me guys. I looked at the schematic again, and CB2 goes to the serial line, but not to the datasette. so they are two different inputs. going back over to see CA1, which is the read pin of the datasette (pin 40 of UBE7, the left VIA on the board). So what does the reference guide say about CA1????

P: PORT LATCH ENABLE
As long as this bit is 0, the PORT register will directly reflect the
data on the pins.
If this bit is set to one, the data present on the input pins of PORT A
will be latched within the chip when the CA1 INTERRUPT FLAG
is set, As long as the CA1 INTERRUPT FLAG is set, the data on the
pins can change without affecting the contents of the PORT
register. Note that the CPU always reads the register (the latches}
rather than the pins.
Input latching can be used with any of the input or output modes
available 1 or CA2.

So this bit should be set to 0 definitely!!!
This is bit 1 of $911B.

Next, where is the CA1 data held??
Well, it says PORT A...so where the hell is that?

Just to observe it, I would go with $911F, non-handshaking.
or if you want handshaking, it is address $9111.

PORT A I/O REGISTER
These eight bits are connected to the eight pins which make up
port B. Each pin can be set for either input or output.
Input latching is available on this port. When latch mode js
enabled the data in the register freezes when the CB1 interrupt flag
is set. The register stays latched until the interrupt ftag is cleared.
Handshaking is available lor output from this port. CB2 will act as
DATA READY SIGNAL. This must be controlled by the user
program, CB1 acts as the DATA ACCEPTED signal, and must be
controlled by the device connected to the port. When DATA
ACCEPTED is sent to the 6522, the DATA READY line is cleared,
and the interrupt flag is set.

You can also turn off the shift register at 911B on the auxiliary control register. There are many random options.

So, uh...what do you do with that? OH there was something I missed! The IFR is the master controller if you like for all these
registers.

Bit 2 of the IFR (interrupt flag register) is active when there is an edge trigger.
bit 3 of IFR is active when the shift register is modified.
Where is the interrupt flag? Address $911D

Personally, I'd just wire up pin 40 to a known user port in and then bit bang it and use the jiffy clock. but I am lazy. If you could use
this confusing set of registers and bits to make it work, it would be even better, no soldering required.

Anyway, CA1 is where the read data bits come in. that is at 911F and 9111. Beyond that there is a universe of options for that VIA chip...After looking at that for an hour, I think it is very aptly named. As such, for the control part, check out the random assortment of bits on 218-226 of the programmer's reference guide.

[srowe]

The tape interface (like the serial bus and RS232) is implemented by bit banging, it does not use the shift register of the 6522. In fact the shift register has a bug that affects shifting in.

[nippur72]

@Forbidden64 if you remember the name/site of the italian guy it would be very very interesting. I hope the site is still there.

Are there any fast loaders for the VIC ? We could look into them and see how they work. Or perhaps we could look at the LOAD kernal routine (and compare it to C64's).

[nippur72]

@Forbidden64, was him Luigi Di Fraia ?

[ops]

Are there any fast loaders for the VIC ? We could look into them and see how they work. Or perhaps we could look at the LOAD kernal routine (and compare it to C64's).

I have disassembled Anirog fast loader, see

https://github.com/ops/anirog-copy