DarwinNE wrote: ↑Fri Apr 28, 2023 4:26 pm
Interesting. What are you measuring, exactly? The ouput DC voltage? Where, exactly on the schematic? In this version, there is a CD blocking capacitor on the ouput, C11:
I'm measuring the DC voltage at the pin of the VIC, whilst there's a TV connected to the AV DIN socket. This is so I can reproduce the horrible audio behaviour of the VIC in the FPGA I'm working on.
The graphs were produced using a limited number of data points, so I'm going to fill out the table (256 entries! Yippee!) and then graph it in different ways to see if I can refine my "acoustic model" to sound less like a kazoo being put through a meat grinder. I could use a simple lookup table, but that would use 32kb of FPGA memory, and I'm not certain I can afford to use that much.
Each voice has three output states:
- Disabled (doesn't contribute anything to the output signal)
Low, which drives the output signal lower by a modest amount
Hi, which drives the output signal higher by a less modest amount.
There's a steady DC offset of around 2.4V, and the volume control adds Vol/10 volts to the output regardless of what the voices are doing - even if they're all disabled. It the 0..15 value of the volume control is used as a multiplier of ((number of high outputs * high scale factor) - (number of low outputs * low scale factor)), so the final sound equation I WAS using was
2.4 + vol/10 + nHI * HIscale * vol - nLO * LOscale * vol
This sounds awful. Hence my desire to map the whole range, graph them all and scrutinize what I'm doing wrong (because I am doing this wrong - it makes sounds at the right frequency, but the clipping is badly wrong, so everything coming out of the speaker is clipped. I'm fairly certain that my fixed-point arithmetic in the FPGA is wrong, plus the scaling of "output voltage" to "value to poke into the DAC" might be another issue.