Aliases

[JonBrawn]

I ran into this today:

The VIC 6560 is visible at addresses $9000 - $900F

However, the address decode inside the 6560 only decodes address lines A13 down to A8, so the VIC will respond to any address in the range of $9000 - $90FF, with the 16 registers being aliased 16 times. I was verifying this, and I discovered that yes, you could write to the 6560's registers through these 256 alias addresses, but reads returned "other values," bearing no similarities to the equivalent values read from $9000-$900F. It turns out that the PIAs are only partially decoded, so the first one, which is usually said to be at an address of $9110, also has aliases at $9010, $9210, and $9310. Likewise, the second has aliases at $9020, $9220, and $9320. So in the case of trying to read from the VIC via addresses $9010 - $901F, you are reading from both the VIC and the first PIA, and writing to that address range updates both the VIC and the PIA, which is probably not what you're looking for except for extremely specialized situations.

How bad is it to have both NMOS devices driving the bus in opposite directions? My system appears to have survived the ordeal, but it's not something I'm going to make a habit of doing.

[Mike]

Just to note, those are 6522 VIAs, not PIAs.

Within I/O 0 (i.e. $9000..$93FF), VIC-I selects itself in the range $9000..$90FF (actually, it has an own address comparator for the range $1000..$10FF on the VA bus), VIA #1 is selected whenever VA4=1 and VIA #2 is selected whenever VA5=1.

That means in the range $9000..$90FF, you see VIC-I everywhere, and the first usable mirrors of VIA #1 and VIA #2 are at $911x and $912x, respectively. There exist holes in I/O 0, where none of the three ICs are selected ($9100..$93FF, and VA4=VA5=0).

Upon register write, you'd write to up to three ICs (whether you want it or not) - upon read, all ICs in question are NMOS technology, and you get a wired-AND of their outputs.

How bad is it to have both NMOS devices driving the bus in opposite directions? My system appears to have survived the ordeal, but it's not something I'm going to make a habit of doing.

When only NMOS (or TTL) devices are in the play, the internal pull-up( FET)s act as current limiting devices, so no harm is done.

As soon as you have CMOS devices around, the situation is more delicate: CMOS outputs can drive both levels, low and high, with a good current. When two of those outputs play tug-of-war there (one low, one high), you short these which leads to increased power dissipation, an undefined logic level on the signal line, and in whole this can damage both chips within short time.

See also: Writes to $9010-$901F.

[JonBrawn]

Just to note, those are 6522 VIAs, not PIAs.

That's what you get for authoring at 2:30 in the morning!

actually, it has an own address comparator for the range $1000..$10FF on the VA bus

That's what I was testing - it is not unknown for game and demo writers to access devices through alias addresses (possibly to reduce an address calculation by a cycle or two?), so knowing that there were 15 more aliases of the registers in the VIC I thought I ought to at least test that they work as expected. It turns out that they do, in that reads "don't work."

How bad is it to have both NMOS devices driving the bus in opposite directions? My system appears to have survived the ordeal, but it's not something I'm going to make a habit of doing.

When only NMOS (or TTL) devices are in the play, the internal pull-up( FET)s act as current limiting devices, so no harm is done.

TTL isn't made from FETs - it's made from bipolar junction transistors (BJTs).

which are somewhat more aggressive drivers.

The datasheet for the FETs I'm using as level shifters describes them as having "high saturation current capability", so I'll have to watch what I get up to.

[groepaz]

IIRC in NMOS there is only an active driver to GND, and a pullup to VCC (and that pullup is actually a FET).

However, multiple NMOS outputs driving the bus is a common thing to do and no problem at all - and you want to reproduce that exact behaviour for a drop in replacement of an NMOS IC.

[Mike]

When only NMOS (or TTL) devices are in the play, the internal pull-up( FET)s act as current limiting devices, so no harm is done.

TTL isn't made from FETs - [...]

Note I put the FET part of the sentence in parentheses as well ... ... of course I know TTL uses BJTs.

[but BJTs] which are somewhat more aggressive drivers.

The BJT-switch in the TTL output is easily capable of sinking the current of its own pull-up driver, and it also needs to sink all inputs it is connected with, each of which easily sources current on the order of 1 mA when it "sees" a low-level signal.

It is not unknown for game and demo writers to access devices through alias addresses (possibly to reduce an address calculation by a cycle or two?)

Not unknown, maybe. It is still bad practice, especially if on later models former mirrors are repurposed for additional chips (which happened on the C128). Thus far, I have not used aliased (I/O) addresses in any of my programs for the VIC-20, and it is also unlikely I will ever see the necessity to do so.

However, multiple NMOS outputs driving the bus is a common thing to do and no problem at all - and you want to reproduce that exact behaviour for a drop in replacement of an NMOS IC.

Yet you would preferably use open-collector or open-drain outputs for that.

[groepaz]

Yet you would preferably use open-collector or open-drain outputs for that.

mmmh doesnt "NMOS" imply "open-collector"?

[tlr]

Yet you would preferably use open-collector or open-drain outputs for that.

mmmh doesnt "NMOS" imply "open-collector"?

You can have push-pull, see p3 here: https://www.princeton.edu/~mae412/HANDO ... s/6522.pdf
It's just that most of it is open-drain with an NMOS transistor as pull up.

[Mike]

mmmh doesnt "NMOS" imply "open-collector"?

The answer is a big NO.

First of all, you'd only have open-collector with TTLs, with their BJTs, where in the output stage their switch-to-ground transistor does not have its collector connected to an internal pull-up - hence open-collector.

The equivalent in NMOS logic is open-drain. Here, in the output stage their switch-to-ground FET does not have its drain connected to an internal pull-up - hence open-drain.

In both cases you need an external pull-up resistor to get a defined high level when the output stage does not switch to ground.

Multiple open-collector or open-drain outputs may drive a single signal as wired-AND, and the current is in any case limited by the single pull-up resister that is used. For an example, this is exactly the bus configuration in charge with the CBM serial bus data and clock lines (and the TTL 7406 bus drivers used there are exactly that: open-collector).

[groepaz]

Ah i see. Thanks. Again what learned (as we say in good old germany)

[JonBrawn]

Most of the I/O of the VIC is tri-state and bidirectional. Tri-state can be implemented using a chain of four FETs. How is tristate managed in NMOS?