AAY64 has the following to say in this matter (
link):
Code: Select all
6510/65816 Addressing mode: Absolute (R-M-W) -- a
(ASL,DCP,DEC,INC,ISB,LSR,RLA,ROL,ROR,RRA,SLO,SRE,TRB,TSB)
(3 bytes) (6 and 8 cycles)
+---------------+------------------+-----------------------+----------+
| Cycle | Address Bus | Data Bus |Read/Write|
+---------------+------------------+-----------------------+----------+
| 1 | PBR,PC | Op Code | R |
| 2 | PBR,PC+1 | Absolute Address Low | R |
| 3 | PBR,PC+2 | Absolute Address High | R |
| 4 | DBR,AA | Data Low | R |
| (1) 4a | DBR,AA+1 | Data High | R |
| (12)(3) 5 | DBR,AA+2 | Internal Operation | R |
| (1) 6a | DBR,AA+1 | Data High | W |
| 6 | DBR,AA | Data Low | W |
+---------------+------------------+-----------------------+----------+
(1) Add 1 cycle for M=0 or X=0 (i.e. 16 bit data).
(3) Special case for aborting instruction. This is the last cycle which
may be aborted or the Status, PBR or DBR registers will be updated.
(12) Unmodified Data Low is written back to memory in 6502 emulation
mode (E=1).
See also: Abbreviations
In short: after INC/DEC have read opcode and address, the following sequence reads the value in memory, then -
while internally modifying the value! -
writes back the original value *), and finally, writes the modified value.
If this fails on original hardware and works on VICE, this is something both Jim Brain and the VICE team should be notified of.
tokra wrote:I seem to vaguely remember that using inc and dec on any IO-register (instead of memory) is never really a good idea.
At least that method should be used with caution, yes. Though, some routines use these ghost-writes to an advantage (opening side-borders on the C64 in the presence of sprites comes to my mind), likewise I use
INC $9110 (VIA #1 port B) to cycle the colour RAM bank in my VFLI display routine with no adverse effects.
*) on the later CMOS versions of the 65xx, this was changed to do a
read on the (opcode-)byte following the INC/DEC instruction instead, so there are not anymore stray accesses on possibly even read-sensitive I/O locations