Interrupt triggering

[matsondawson]

It's been difficult to find concrete information on how many cycles an interrupt must be active before it is detected, and how instructions such as CLI, RTI, and PLP affect them, but this is what I think I've worked out.
Can someone confirm it's correct.

1/ An interrupt must be active for at least 2 cycles before the end of an instruction to be triggered.
2/ An interrupt cannot be triggered immediatly after a CLI, RTI, or PLP. i.e. At least one instruction must execute before a new interrupt.
3/ For an interrupt that occurs during a branch, if the branch is taken and it is to a local page, then must be active for an 1 extra cycle to be detected.

[Leeeeee]

That looks like what I remember for recognising an active IRQ. NMI is edge triggered so doesn't need to stay asserted but still needs to be a asserted for a minimum of two cycles.

Another thing to note is that the NMI interrupt must be inactive for at least two cycles sometime after the vector has been taken for a new interrupt to be recognised. This caused problems with 3Com network cards reasserting their interrupt too soon after it was cleared. I got round that by using a D type FF on the NMI input that could be cleared by software before I cleared the interrupt from the 3Com card.

Lee.

[matsondawson]

Ah cool, I'm trying to get Bandits to run on my emulator, it seems to be the only game I can't quite get to work. Does anyone know if it's doing something extra special?

[Leeeeee]

Did a little more looking at IRQ and NMI timing.

IRQ and NMI are sampled at the falling edge of 02 prior to the last cycle of the instruction. For IRQ to be recognised it must have been active for a minimum setup time before this edge which is 200ns for the 1MHz part and 110ns for the 2MHz part. For NMI to be recognised it must have changed at least 300ns for the 1MHz part and 200ns for the 2MHz part before this falling edge.

So for a 1MHz part to guarantee that an IRQ will be seen it needs to stay active for at least 200ns plus the number of cycles of the longest instruction and to guarantee that an NMI will be seen it must stay active for at least 300ns plus one cycle time.

Lee.

[matsondawson]

In the case of PLP, can an interrupt occur on the next instruction if the I register didn't change?

[Leeeeee]

As far as I can tell PLP updates the status register on the last cycle of the instruction so as long as I was clear at the start of the instruction and IRQ is active in time the interrupt will be recognised regardless of the restored state of I.

Lee.

[matsondawson]

Did a little more looking at IRQ and NMI timing.

IRQ and NMI are sampled at the falling edge of 02 prior to the last cycle of the instruction. For IRQ to be recognised it must have been active for a minimum setup time before this edge which is 200ns for the 1MHz part and 110ns for the 2MHz part. For NMI to be recognised it must have changed at least 300ns for the 1MHz part and 200ns for the 2MHz part before this falling edge.

So for a 1MHz part to guarantee that an IRQ will be seen it needs to stay active for at least 200ns plus the number of cycles of the longest instruction and to guarantee that an NMI will be seen it must stay active for at least 300ns plus one cycle time.

Lee.

Ok, I saw that quote in a 65c02 datasheet, but, I've also seen in other datasheets.
- Interrupt is sampled on falling edge of phi2
and
- Interrupt is sampled on the falling edge of phi2 during an opcode fetch

Now in the case of bandits the way to make it work continuously for me is to follow "Interrupt is sampled on falling edge of phi2".

Also for NMI, i've seen NMI as sampled during phi2 not on falling edge.

It'd be awesome if the datasheets could agree!