CPU cycles are to be multiplied by 2 ?

[matsondawson]

I've looked around but can't quite seem to find what I want to know.
From what I've read, the 6502 only accesses memory on every alternate cycle, so when I execute an STA $HHLL, it says in the manual that will take 4 cycles. But it requires 4 memory operations, so wouldn't that be 8 cycles?

[Kweepa]

That instruction is a single "memory operation," storing the (single byte) contents of the accumulator at address $HHLL.
If the manual says four cycles, it means four cycles. Sounds about right.

[Mike]

Indeed the 6502 accesses the bus on every cycle, even when the opcode doesn't suggest so - like TXA, where only the opcode must be read, though it still needs 2 cycles. In those cases, the CPU does another read operation on the last address.

However, half of the cycle time the CPU "ignores" the data bus, i.e. it neither places write operations there, nor does it read (and thus load) the bus. This can be used by another bus master - for example the VIC-I chip - to make an interleaved bus access.

This is how to interpret the phrase "every other cycle" in the manual.

Michael