vic-20 SRQ (CB1) interrupt?

[tschak909]

Hi guys, we have the FujiNet working with the VIC-20 now, but I have a very important question:

With SRQ, I can see it's hooked up to the VIA #2, via CB1.

I am still digging for a good ROM disassembly for the IRQ routine at EABF, but, I thought I'd ask here anyway.

I don't have to explicitly enable the SRQ interrupt on the C64, do I need to do so on the VIC20?

-Thom

[srowe]

VIA#2 IER is setup with all interrupts disabled by default. The tape routines selectively enable timer & CA1 interrupts, the normal jiffy clock also enables T1.

[srowe]

I am still digging for a good ROM disassembly for the IRQ routine at EABF, but, I thought I'd ask here anyway.

How about this?

https://eden.mose.org.uk/gitweb/?p=rom- ... EAD#l10602

[tschak909]

So the correct thing for me to do would be to enable CB1, jump to old IRQ handler, and let the default IRQ handler enable what it needs to do?

-Thom

[srowe]

So the correct thing for me to do would be to enable CB1, jump to old IRQ handler, and let the default IRQ handler enable what it needs to do?

You don't give any context about what you're trying to do but to handle interrupts from the SRQ line you'll need to

1. make sure the CB1 bit in the PCR is set appropriately. The KERNAL sets it to positive edge triggered (i.e. 0 -> 1 transition)
2. add your own IRQ handler that checks the IFR bit and then chains the standard handler
3. set the appropriate bit in the IER
4. set the appropriate bit in the IFR

You cannot directly read the Cx1 lines, only have interrupts on transitions.

[tschak909]

Yup, I understand completely. Just wasn't sure what interrupts the kernal nominally enables and when. With the listing, this is more clear.

-Thom