6560 FPGA Progress.

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Mike
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Re: 6560 FPGA Progress.

Post by Mike »

JonBrawn wrote:However, I'm a bit mystified about why the values I've used work. The value in question is "Delay tap 11". That means I've delayed the visibility of the reverse bit (and just the reverse bit) by twelve ticks of the fast clock (taps 0 to 11). The fast clock is the clock you get when you notionally XOR the two 14.318181 MHz clock phases together [...]
I'd suspect Phi1_IN (Pin 39) xor Phi2_In (Pin 38) === TRUE except for extremely small glitches at the positive/negative edges of both signals as they're inverses of each other. VIC-I internally probably uses either the positive or the negative edge of both inputs ORed to derive the pulse train for the fast clock.
[...] - it zips along at 28.636363 MHz and is used so that the dot clock comes out as a whole multiple, seven cycles of the fast clock. The 14.318181 MHz clock isn't good enough for this purpose, as the dot clock would have to be 3.5 cycles... but I digress. So, the reverse bit is delayed by 12 of these fast_clk cycles. A pixel, as mentioned, is seven fast_clk cycles.
Yes. Unlike PAL, where pixel clock and colour carrier are the same (4.43 MHz), the NTSC VIC-I derives the colour carrier frequency by dividing the fast_clk by 8, which gives 3.57 MHz.
A single cycle of the CPU clocks is 28 fast_clk cycles. 12 fast_clk cycles aren't anything that I can think of as being relevant.
There's the timing circuit formed by U2 and U3 which adds some gate delays on the mainboard until VR/W is fed back to VIC-I. I'd think you get some relevant nanoseconds extra delay where VR/W goes "write"->"read" upon end of the CPU write cycle into the colour register, which gives a "not quite one" pixel delay for the colour changes. At least that's where I would start my investigations. As I wrote earlier, the issues at hand would be easier to understand with a full reversing of the original chip layout.
I'm still working on this - I'm pulling together a new interface board for a different FPGA (one that money CAN buy), and once I've got that up and running, I'll need to get some child labour in to play games and spot things that aren't right.
... :mrgreen:.

bjonte's recent release of H.E.R.O. provides a nice new test case. :)
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Re: 6560 FPGA Progress.

Post by tlr »

JonBrawn wrote: Sat Dec 31, 2022 11:14 pm I'm still working on this - I'm pulling together a new interface board for a different FPGA (one that money CAN buy), and once I've got that up and running, I'll need to get some child labour in to play games and spot things that aren't right.
Nice! Which FPGA are you looking at?
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Re: 6560 FPGA Progress.

Post by JonBrawn »

tlr wrote: Sun Jan 01, 2023 11:18 am
JonBrawn wrote: Sat Dec 31, 2022 11:14 pm I'm still working on this - I'm pulling together a new interface board for a different FPGA (one that money CAN buy), and once I've got that up and running, I'll need to get some child labour in to play games and spot things that aren't right.
Nice! Which FPGA are you looking at?
Trion T20 is my current favourite, as you can actually buy them without having to suffer the scalping practices of eBay.
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Re: 6560 FPGA Progress.

Post by tlr »

JonBrawn wrote: Fri Jan 06, 2023 9:13 pm
tlr wrote: Sun Jan 01, 2023 11:18 am
JonBrawn wrote: Sat Dec 31, 2022 11:14 pm I'm still working on this - I'm pulling together a new interface board for a different FPGA (one that money CAN buy), and once I've got that up and running, I'll need to get some child labour in to play games and spot things that aren't right.
Nice! Which FPGA are you looking at?
Trion T20 is my current favourite, as you can actually buy them without having to suffer the scalping practices of eBay.
Looks quite interesting, not too expensive. Supports running under linux which is nice. A little vague on the VHDL support which I prefer but if you are doing verilog it seems to be fairly complete on paper at least.
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Re: 6560 FPGA Progress.

Post by JonBrawn »

Well, that's been a hard month. Poor health and a mad rush at work have kept me from the project, but boards and components have been ordered now, so let's see what happens. I've got some 48-pin (I think), 0.5mm pin pitch DIL packages to solder (3 of them), so that'll be interesting - Does anybody want to offer advice? Other than "get someone else to do it"?
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Re: 6560 FPGA Progress.

Post by tlr »

JonBrawn wrote: Fri Feb 03, 2023 12:37 am Well, that's been a hard month. Poor health and a mad rush at work have kept me from the project, but boards and components have been ordered now, so let's see what happens. I've got some 48-pin (I think), 0.5mm pin pitch DIL packages to solder (3 of them), so that'll be interesting - Does anybody want to offer advice? Other than "get someone else to do it"?
Are you sure you mean DIL?

If I'm guessing, 48 pins and 0.5 pin pitch, could that be a TSSOP48? Perhaps a flash?
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Re: 6560 FPGA Progress.

Post by JonBrawn »

"DIL" as in Dual In Line, yes, it is really an SOP<mumble>, with two rows of pins rather than a square with pins on every side. It's a 16-bit bi-directional level shifter, and all 48 bits are used! This board is another interface between an FPGA development board and the VIC-20's 6560 socket, so I can get the code and programming of the FPGA right while in parallel trying to get the mix of extra guff that goes with an FPGA sorted out.
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Re: 6560 FPGA Progress.

Post by tlr »

One technique you should look for is drag soldering/smear soldering. I've never done this myself, but I've seen it done. The general idea is to put solder on by dragging along the pins and relying on capillary action to get the solder to where it is supposed to be. You probably want a decent solder mask, i.e between the pins, for this to work correctly. For 0.5 pitch I strongly suggest a microscope or at least some kind of lupe, unless you’re 20 perhaps. :)

This is a good overview of extremely professional work: Professional SMT Soldering: Hand Soldering Techniques - Surface Mount

This is an example of soldering a 0.5 pitch TSOP-style part using fairly normal tools: SMT Hand soldering of 38 pin TSSOP with 0.5mm pitch

Masking sensitive neighboring parts with kapton tape like seen in the first video is clever I think.
Last edited by tlr on Sat Feb 04, 2023 7:46 am, edited 1 time in total.
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Re: 6560 FPGA Progress.

Post by beamrider »

https://www.youtube.com/watch?v=Nq5ngauITsw

These are by far the best soldering videos I've seen (professionally produced). This is lesson 9 but all 9 are worth watching.
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Re: 6560 FPGA Progress.

Post by beamrider »

tlr wrote: Sat Feb 04, 2023 5:19 am This is an example of soldering a 0.5 pitch TSOP-style part using fairly normal tools: SMT Hand soldering of 38 pin TSSOP with 0.5mm pitch
They make it look so easy!
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Re: 6560 FPGA Progress.

Post by Lambda_BM »

Following this now. I’ve read through most of this thread and am very excited to see the result, as I have a early NTSC Vic that has a cooked Vic chip. Ordered another to find out that one was dead as well! Looking forward to seeing the future progress!
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Re: 6560 FPGA Progress.

Post by JonBrawn »

tlr wrote: Sat Feb 04, 2023 5:19 am Masking sensitive neighboring parts with kapton tape like seen in the first video is clever I think.
My dog ate my Kapton tape just yesterday. She also ate orange electrical tape, the plastic handle of my best stubby screwdriver, something white, and I caught her just before she broke into the flux pen.

It would seem I didn't click the door to my "laboratory" (aka "the spare room") closed properly.
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Re: 6560 FPGA Progress.

Post by JonBrawn »

On a technical note, I soldered down the 3 level shifter chips with no shorts or opens, Only To Realize I'd soldered one the wrong way round, so I removed it with hot air. I soldered it back down again the right way round, Only To Realize I'd transposed the Output Enable and Direction pins in the schematics. I lifted the legs and spent considerable time messing with green wire, which was an utter failure. I tried many ways to attach the wires to the chip's legs but could not get it to work. The closest I came to success was glueing the wire to the chip package and then having the springiness of the wire hold it against the leg while I tried to apply the tiniest amount of solder. Note to self: don't use hot melt adhesive near something you will solder. I gave up at that point - I can solder the chips to the board, but I can't do rework.

There are other issues with that board, so I will respin it and take the opportunity to add some debug stuff (pins for connecting a logic analyser, "feature select" jumpers and the such).
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Re: 6560 FPGA Progress.

Post by JonBrawn »

History and technical info about what I've done so far: https://www.youtube.com/watch?v=fZqIlUJzN74
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Re: 6560 FPGA Progress.

Post by mathop »

Very good video.
The VIC (6560/6561) in fact has sepearate luma resistors for each colour, see for example this thread (partly in German)
https://www.forum64.de/index.php?thread ... ost1699320

I think it also may have been discussed on this forum, probably somewhere in here:
http://sleepingelephant.com/ipw-web/bul ... php?t=8733

The VIC-II is the one with the limited luma levels, starting with five in the 6569R1/6567Rsomething and then nine later.
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