It's similar at what I'm thinking, but my "pages of stored datas" are not deep 1k (I/O3), but it's deep 8k (BLK 5) so my register for paging has to be 3bit deep for define 8pages.If the register's bit 7b=0 (startup) then the BLK 5 is "ROM over RAM":if you read on BLK5 you will read from the selected pages of ROM, but if you write on BLK5 you will write on the covered RAM, than concettually (on BLK5) you can "LDA" and "STA" into the same address and at the end BLK5 RAM will be the copy of the selected page of ROM.Mike wrote: ↑Sun Dec 20, 2020 7:22 am (...)
In any case, you would use part of I/O x to hold paged ROM data (say, I/O 2 to transfer 1K pages in one go), from which BLK1..3 (and eventually BLK5) are filled (...)
You'd need an 8 bit latch register for the upper address lines of the (E)EPROM, the register which would be located in I/O 3. 6 bit would map in one of the 1K pages of the (E)EPROM into I/O 2 (used for the startup procedure), at least 1 bit selects between ROM or RAM in BLK5. Plus some glue logic.
Is this more like what you're up to?
At the end of the all copy process the register's bit 7b will set: the BLK5 8k ROM window will disappear and the BLK5 RAM will be present (standard behaviour: read & write).
This implémentation make architecture easy and flexible: a sw developer can use unused ROM pages as multiple banks of datas (on BLK5) 8k deep (as datas for new game levels....) similarly to loading from a disk the BLK5 area, but without accessing any peripherals.....
And at power up: ROM will be find (read) on BLK5 for the cartridge "auto start key"....