eslapion wrote: ↑Thu Dec 19, 2019 7:29 am
You need the CLK signal only when using static RAM and only because the stupid TED stretches the CAS and R/W (...)
PLUS4 use the same architecture and CPU that is used into the C16.
Into a PLUS4 inside the shield box you can find a TED chip, the same chip that is not compatible with saruman-ted without connecting the CLOCK line....
So you just told exactly what I told in my precedent post...
I have warned about a problem, I don't want to do more, I have not responsibility about if/why/when your projects work, I can only friendly communicate my perplexity, like I did on saruman-TED.
eslapion wrote: ↑Thu Dec 19, 2019 7:29 am
You need the CLK signal only when using static RAM and only because the stupid TED stretches the CAS and R/W into the the following half cycle where the low addresses (sometimes) shift for the refresh cycle. So you only get problems after a CPU write and only IF it is followed by a refresh cycle.
There is more than one solution to this problems and using an inexpensive OR gate with the CLK-R/W signals happens to be one of the least expensive and simplest solution but it's really not the only one. I know of at least 3.
Thanks for worrying about me, but don't worry, it's a FACT that I know how '264, static & dynamic RAM work: my project worked at first shot......
Whoa... the master has spoken! This is the way! I'm happy my project didn't work at first try. It forced me to look deeper into how the TED works and learn more from it. Unlike you, I disclosed my findings for everyone's benefit. Well, what if I made you, just for you, a C16 expansion that doesn't use the CLK signal and works perfectly well ? Very easy, just like Saruman-64, latch the lower addresses when RAS=0... The DRAM doesn't receive the CLK signal and it doesn't need it because it latches the address lines. It's the only difference with static RAM.
HAVE A GOOD LUCK
"Two things are infinite, the universe and human stupidity, and I am not yet completely sure about the universe." (Albert Einstein)
eslapion wrote: ↑Thu Dec 19, 2019 7:29 am
You need the CLK signal only when using static RAM and only because the stupid TED stretches the CAS and R/W (...)
PLUS4 use the same architecture and CPU that is used into the C16.
Into a PLUS4 inside the shield box you can find a TED chip, the same chip that is not compatible with saruman-ted without connecting the CLOCK line....
So you just told exactly what I told in my precedent post...
HAVE A GOOD LUCK
I never said the Plus/4 was any different from the C16 in the way it accesses RAM.
The Plus/4 has the same problem as the C16; it stretches the CAS low and R/W low into the following half cycle where the low addresses (sometimes) shift. You can either cut off the RAM access which the OR gate does or you can latch the addresses.
Since Saruman-64 is designed to replace DRAM ICs, it latches the addresses. Saruman-TED is designed to be directly attached to a non-multiplexed bus so it cuts off the RAM access before the end of the CAS signaling. BOTH WORK FINE!
Saruman-TED will work directly in both the C16 and Plus/4 with no modifications. Saruman-64 can work in both the Plus/4 and the C16 too if you re-attach A14 and A15 to the 74LS257 multiplexers, as you would for a DRAM 64k expansion.
brain wrote: ↑Fri Dec 20, 2019 12:49 am
My simplistic contribution...
The idea is good but there is a technical hurdle.
In the Plus/4 and C64 boards 250407, the spacing between the DRAM ICs is reduced. The design you showed should work fine on boards 250425 and the old 326298.
brain wrote: ↑Fri Dec 20, 2019 12:42 pm
Hmm, I thought they all uses 4464s... OK, I'll pull one out and measure it. I might be able to make one board with different hole patterns...
Jim
The Plus/4 and C64 boards 326298, 250407, 250425 and the SX-64 all use 8 DRAM ICs type 4164 and they all have the same narrow DIP footprint but the spacing between the footprints varies.
The spacing on the Plus/4 is nearly identical to that used on C64 board 250407 but not perfectly identical.
