Not quite... The end of the ROM based PLA for the 64

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e5frog
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Post by e5frog »

Perhaps they have good theoretical knowledge but haven't actually tested it for real.
I'm guessing they would still claim there's a risk something doesn't work because of some "well known fact" that everyone is supposed to know. ;-)

I'd have to look through all threads again to check the arguments I didn't understand. I remember something about "bus contention". I understand it as there's crap on the bus that isn't supposed to be there at that particular moment but didn't quite get why it would appear.
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Post by eslapion »

e5frog wrote:Perhaps they have good theoretical knowledge but haven't actually tested it for real.
I'm guessing they would still claim there's a risk something doesn't work because of some "well known fact" that everyone is supposed to know.
In most dictionnaries, that's called arrogance.
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Post by e5frog »

Too bad they couldn't explain it better or pointed to some physics page or similar. Would be interesting to look into the details why an "eprom can never replace a logic circuit". And also why they call eprom a poor mans PLA.

Wikipedia says this:
http://en.wikipedia.org/wiki/Programmable_logic_device

1 they are usually much slower than dedicated logic circuits,
2 they cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's outputs may glitch as the inputs switch,
3 they consume more power,
4 they are often more expensive than programmable logic, especially if high speed is required.

1 Doesn't seem to be a problem in the C64
2 I guess this is the key question, however it says "may"
3 Seems in our case the eprom is a lot cooler which leads me to believe it's a lot less power hungry.
4 Nope not in this case.

So regarding point 2, does fiddling with all the inputs in a C64-ish manner generate any glitches on the output? Is this perhaps only true for older types of eproms, from when before PLA:s were invented?



BTW, it's annoying there is a narrow narrow editing area when writing but when watching the threads here at Denial they are as wide as is possible, using a WS screen makes thing annoyingly wide to read.

So it's too bad for that reason that you posted it here. Would be nice getting it as a pdf, a professional looking report. ;-)
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Post by eslapion »

e5frog wrote:Wikipedia says this:
http://en.wikipedia.org/wiki/Programmable_logic_device

1 they are usually much slower than dedicated logic circuits,
2 they cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's outputs may glitch as the inputs switch,
3 they consume more power,
4 they are often more expensive than programmable logic, especially if high speed is required.
The thing is, between the Commodore 64 and today's PROM circuits, there are 25 years of evolution.

The result is today's ROM circuits are actually slightly too fast to act as a 64's logic device.

As for the PDF file you're referring to, I simply want to make sure there are no major errors on what I posted here before I do it.

Also, regarding point 2, the people who wrote the article are careful to specify they cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's outputs may glitch as the inputs switch.

Many older EPROMs do. For example, the MCM68766, which is one rare type that is pin compatible with Commodore's 2364 ROMs does. Its even funny because assuming you keep the !CS line low while shifting the input, it will very quickly output the right value, then shift to multiple invalid values for about 150ns then go back to the right value.

Later generations of AMD EPROMs which could be used as a PLA because they're rated for 100ns also do something similar. These could be very unsafe when used as a PLA.

However, as you can see, the M27C512-90B6 doesn't and AFAIK, the Atmel doesn't but its too fast for CAS.
Last edited by eslapion on Sun Dec 18, 2011 9:18 am, edited 1 time in total.
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High Scores, Links, and Jeff's Basic Games page.
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[MOD] User "Jeff" is advised not to spam anymore, or his IP will be banned :P .
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Post by eslapion »

e5frog wrote:So it's too bad for that reason that you posted it here. Would be nice getting it as a pdf, a professional looking report. ;-)
It will be titled:

The Commodore 64’s PLAgue
Mythbusting the claims about bus contentions and PROM based PLA substitutes: A low level investigation by François Léveillé
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Post by e5frog »

:-D
Nice one.
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Post by Kananga »

eslapion wrote:I guess they're too busy chatting with the psychiatrist and discussing the change in medication.
Actually I wouldn't mind discussing their medication with some of them. Of course I am not a psychiatrist. I could read answers off Eliza though.
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Post by eslapion »

Since this thread was posted, a lot of people asked for sources of the M27C512-90B6 since it is now actually out of production.

Future Electronics with headquarters located here in Montreal apparently has about 67'000 of them in stock and sells them for about $2.50$ each. Cheaper if you buy larger quantities.

Link:
http://www.futureelectronics.com/en/tec ... -90B6.aspx

Sometimes they can be found on ebay but they are rare and rather expensensive.

Also, as I have mentioned elsewhere, the M27C512-90F6 is actually exactly the same chip as the M27C512-90B6 but it has a ceramic package and window which makes it erasable and easier to damage when soldering. However, the -90F6 is sometimes less expensive and easier to find on ebay and other places than the -90B6.

See items 160619903170 and 150720757197 on ebay.

If you have found a chip, still in production, from another company that has characteristics similar to the M27C512-90X6, please feel free to post about it here.

I will also take the liberty to respond here to something posted on another forum as the thread was locked after flammatory verbal attacks.
According to "Admiral Decker" the problem is not with speed of the chip you are using but a problem with the 64. Take a look at his love letter to me on his site and you'll find it.
I couldn't care less for the love letter but generally, "Admiral Decker" is perfectly right.

I believe I mentioned elsewhere that the PLA is a sort of quickly thrown togethere logic "patch" with logic components having different response speeds.

As a memory chip only has one generally fixed response speed, finding one which is within the "sweet spot" of most different generations of C64 is usually a matter of luck. The M27C512-90B6 is such a chip but I have to assume there are others out there.

However, the bus contentions which were used to justify a public drum-beating targeted at me over the last year is, as demonstrated above, virtually non existent on just about all modern technology memory chips, ROM, PROM or otherwise.

Some flash memory chips can also be used as a subsitute to the PLA, assuming they have the proper response speed and there will be no problems whatsoever.

The best thing to do is, just like I did, to check it out with a good scope or logic analyser.

ADDED EDIT:
After examination, the M27C512-90F6 is not at all the same chip as the M27C512-90B6. The level of compatibility is much lower.
Last edited by eslapion on Thu Jun 04, 2015 10:39 am, edited 1 time in total.
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Post by skoe »

eslapion,

While writing an article about the C64 PLA I stumbled over your article here. It's a very good, systematic work. I also checked several PLAs and replacements and came to the same result as you: The M27C512-90B6 is better than its reputation. It works on most C64 boards with several extensions tested and I also didn't find any unusual glitches. I also checked it with my external KERNAL cartridge, which has certain timing requirements. It worked without problems.

Note: This is not the result for any random PROM PLA replacement, but for this very type only. We found lots of C64s out there which failed at this or that and it turned out that they had a bad PROM PLA replacement. I think these experiences made some people (including me) very skeptical. You also mentioned that it depends on various properties of the PLA if it works well or not.

The result of your article are clearly explained and I can confirm most of it. Please don't take it personal that I have some remarks about a few mistakes and questions:
As said earlier, the Commodore made PLA is a clone of something that existed before. It is simply improved over the original and is about twice faster
Twice faster? Did you measure the actual values? Or do you mean the rating? Do you know a rating for the CSG parts?

You make all your measurements with a threshold voltage of 2V. Actually it's about 1.3V for the NMOS chips used in the C64. However, it makes no big difference. All measurements I did used a threshold voltage of 1.5V and came to similar results as yours.
Excuse my naivety but aren’t the half cycles of the CPU and VIC-II supposed to last about 500ns each?
Yes, they are. But you forgot that in these cycles a lot of work has to be done. The addresses are not set up right at the beginning of the cycle. It gets worse because of the bus multiplexing in the C64. But I think you realized this already.
There are negative stutters on cycles where the kernal ROM is accessed and positive ones on cycles where the 6510 is turned off
Same explanation here. Unfortunately you don't have Phi2 on your captures, but I guess that these spikes are at the very moment when the bus control changes from CPU to VIC and vice versa. In that time some address lines are floating and pulled up slowly by resistors only, leading to intermediate states which are also decoded by the PLA.
NMOS technology, which uses transistors to drive a signal from 5V to 0V but uses a resistor to drive a signal from 0Vto 5V. This means every time the PLA is sending a 0V signal, it does so by shorting a resistor between the ground line and the 5V line, effectively turning it into a small heating element.
Well, this is half-true for internal logic. There we don't have resistors but depletion mode FETs, which have a similar but not identical function. And by the way this is even not the case for all internal logic, but for most of it.
This also means a signal transition from 0 to 5V will take much more time than a transition from 5V to 0.
This is also not generally true (despite the fact that it never rises to 5V ;) ). An NMOS inverter (and also other gates) can be tuned by many means: The ratio between pull-up FET and pull-down FET can be changed, this changes the inverter voltage and also t_up and t_down. Super buffers can be used when both edges must become steep. And bootstrap circuits can be used to push a gate voltage above VDD, which speeds up the low => high edge significantly.

Probably you refer to an NMOS output here: For this it's even less true: An NMOS pad driver uses a normal Totem Pole driver with huge FETs. But as they don't have a bootstrap circuit usually, you get the effect you mean: The closer the output voltage comes to VDD - Vth, the less drive (I_ds) the pull-up FET (N-Channel!) has. When the output voltage is low (e.g. lower than 2 V) the driver has a similar strength then in the other direction. Only when the voltage is above 2 or 3 V the current is much lower, leading to a very slow rise time at the end. The final output level is about 5V - 1.3V, because there the current goes towards 0.

This means that the ramp time 5V => 1.3V is roughly the same as 0V => 1.3V for output drivers. Roughly means something like +/- 5 ns, which plays no role at all considering cycle times in the ball park 500 ns.

These effects can also be seen on your captures.
Clearly this is something caused by the signals fed into the PLA and not the PLA itself.
Indeed.
unless you combine a very fast kernal with the slow original CG
That's true. Don't forget cartridges which my use very fast CPLDs and CMOS RAMs etc. That's one of the resons I added these 100 Ohm resistors in the data lines of my cartridge designs: To reduce current peaks because of these effects.
After all, the M27C512-90B6 is rated for a response speed of 90ns.
> Perhaps adding a capacitor on the CASRAM output of these chips to increase the transition time could do the job of delaying the signal.
This may be needed on some boards, yes. My own M27C512-90B6 has an actual propagation delay of about 20 ns, it refuses to work with my KU board, probably because of the lower propagation delay compared to other PLAs.

Note, if you add a capacitor there, you should do it on all outputs. Otherwise you create the chip select overlap ;) Well, CBM made this with their CASRAM RC delay already :/
Sure enough, when measuring the 5Vdc load on the PSU, it shows a healthy 1.25A when using the MOS 906114-01. It rises to 1.32A with the 82S100. However, the M27C512-90B6 turns the 64 into a lean machine at only 1.12A.
Oh, that's an interesting experiment! I'll do the same with my machine. Thank you for the inspiration :)
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Post by eslapion »

skoe wrote:While writing an article about the C64 PLA I stumbled over your article here. It's a very good, systematic work. I also checked several PLAs and replacements and came to the same result as you: The M27C512-90B6 is better than its reputation. It works on most C64 boards with several extensions tested and I also didn't find any unusual glitches. I also checked it with my external KERNAL cartridge, which has certain timing requirements. It worked without problems.
You are most welcome! Thank you for taking the time to read and investigate what I wrote.
skoe wrote:The result of your article are clearly explained and I can confirm most of it. Please don't take it personal that I have some remarks about a few mistakes and questions:
I don't take it personnally. I am glad somebody took the time to take a close look at what I wrote and comes to similar conclusions.

If you spotted a few errors then I'm glad I'll learn something new by your scrutiny.
As said earlier, the Commodore made PLA is a clone of something that existed before. It is simply improved over the original and is about twice faster
Twice faster? Did you measure the actual values? Or do you mean the rating? Do you know a rating for the CSG parts?
These are actual measured values. The actual numbers are provided in the section named a CAStrating issue.
eslapion wrote:On the 82S100, when the CPU accesses the RAM, there is a 40ns delay between CAS being pulled low on the input of the PLA and the CASRAM output reflecting this change. This delay falls to 28ns on the MOS 906114-01, the chip which is said to work with all 64s. The M27C512-90B6 takes 24ns to reflect the same change.
You make all your measurements with a threshold voltage of 2V. Actually it's about 1.3V for the NMOS chips used in the C64. However, it makes no big difference. All measurements I did used a threshold voltage of 1.5V and came to similar results as yours.
I defined the threshold value per John F. Wakerly's Digital Design university course book but NMOS is not among the technologies mentioned in that book. This is just a general guideline which outlines the difference between TTL and CMOS electrical levels to define a valid 0 and 1.
Excuse my naivety but aren’t the half cycles of the CPU and VIC-II supposed to last about 500ns each?
Yes, they are. But you forgot that in these cycles a lot of work has to be done. The addresses are not set up right at the beginning of the cycle. It gets worse because of the bus multiplexing in the C64. But I think you realized this already.
I did. I assume the stutters found when looking at some outputs of the PLA are caused by the demuxing activity.
There are negative stutters on cycles where the kernal ROM is accessed and positive ones on cycles where the 6510 is turned off
Same explanation here. Unfortunately you don't have Phi2 on your captures, but I guess that these spikes are at the very moment when the bus control changes from CPU to VIC and vice versa. In that time some address lines are floating and pulled up slowly by resistors only, leading to intermediate states which are also decoded by the PLA.
I don't have the luxury of a 4 channel scope but my conclusion is the same as yours.
NMOS technology, which uses transistors to drive a signal from 5V to 0V but uses a resistor to drive a signal from 0Vto 5V. This means every time the PLA is sending a 0V signal, it does so by shorting a resistor between the ground line and the 5V line, effectively turning it into a small heating element.
Well, this is half-true for internal logic. There we don't have resistors but depletion mode FETs, which have a similar but not identical function. And by the way this is even not the case for all internal logic, but for most of it.
Interesting. I assume a configuration like that still results in a faster transition from high to low than the other way around.
This also means a signal transition from 0 to 5V will take much more time than a transition from 5V to 0.
This is also not generally true (despite the fact that it never rises to 5V ;) ). An NMOS inverter (and also other gates) can be tuned by many means: The ratio between pull-up FET and pull-down FET can be changed, this changes the inverter voltage and also t_up and t_down. Super buffers can be used when both edges must become steep. And bootstrap circuits can be used to push a gate voltage above VDD, which speeds up the low => high edge significantly.

Probably you refer to an NMOS output here: For this it's even less true: An NMOS pad driver uses a normal Totem Pole driver with huge FETs. But as they don't have a bootstrap circuit usually, you get the effect you mean: The closer the output voltage comes to VDD - Vth, the less drive (I_ds) the pull-up FET (N-Channel!) has. When the output voltage is low (e.g. lower than 2 V) the driver has a similar strength then in the other direction. Only when the voltage is above 2 or 3 V the current is much lower, leading to a very slow rise time at the end. The final output level is about 5V - 1.3V, because there the current goes towards 0.

This means that the ramp time 5V => 1.3V is roughly the same as 0V => 1.3V for output drivers. Roughly means something like +/- 5 ns, which plays no role at all considering cycle times in the ball park 500 ns.

These effects can also be seen on your captures.
I was referring to the output. Thanks for the clarification.
unless you combine a very fast kernal with the slow original CG
That's true. Don't forget cartridges which my use very fast CPLDs and CMOS RAMs etc. That's one of the resons I added these 100 Ohm resistors in the data lines of my cartridge designs: To reduce current peaks because of these effects.
I would be very much interested in looking at the schematics of your designs.

I was mentioning this specific problem because a lot of people are now buying JiffyDOS and have it installed in a modern ROM eliminator instead of a legacy PROM or EPROM. I suspect this product, as a kernal substitute, is much faster than the original chip and it does not incorporate any protection resistors. Therefore, it is likely to cause short bus contentions everytime a slower chip, such as the CG or DRAM is accessed followed immediately with an access to the faster kernal replacement.

Thank you very much for commenting on this thread. A happy new year to you.
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Post by eslapion »

eslapion wrote:...
Also, as I have mentioned elsewhere, the M27C512-90F6 is actually exactly the same chip as the M27C512-90B6 but it has a ceramic package and window which makes it erasable and easier to damage when soldering.
Well, it seems I was totally wrong about this one.

The 90F6 was tested and failed to operate properly on various Commodore 64 which work perfectly well with the 90B6.

Some engineers in the past have claimed EPROMs and PROMs are usually exactly the same type of chip except there is no window for erasing. Clearly this is not the case here.

If you want the real deal then you need a M27C512-90B6.
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Post by eslapion »

Skoe posted a very thorough document about the C64 and PLAs here:
http://skoe.de/docs/c64-dissected/pla/c ... d_a4ss.pdf

It includes extra information about the M27C512-90B6 and other legacy versions of the PLA.
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Re: The end of the ROM based PLA for the 64

Post by eslapion »

After reviewing Skoe's extensive document, it appears my claims about the C64 drawing less power when using the M27C512-90B6 were right but not for the reasons I expected.

It is the M27C512-90B6 itself that takes about 90mA less than an original PLA.

This nice little chip also worked better than original PLAs on a few SX-64 machines as outlined by craftsman1234 on Lemon64 (Supermarket section).

I still have about 60 chips left after acquiring a few more.
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