According to my book here - normal LDA absolute uses 4 cycles where as Zero-page is only 3 cycles.
Yet, when they're indexed they both are listed as executing in 4 cycles - is this correct? I'm using the CBM debugger and it's confirming that this is the case.
Why is LDA/STA Absolute,X as fast ZeroPage,X?
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Why is LDA/STA Absolute,X as fast ZeroPage,X?
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Re: Why is LDA/STA Absolute,X as fast ZeroPage,X?
what you are seeing there is an optimization.... if (and only if) the result of adding X to the low byte of the address does NOT result in a carry over to the high byte, then the 5th cycle can be omitted. consequently if that is the case, then you will observe lda abs,x actually takes those 5 cycles. (your book should mention "penalty cycles" or something alike ... if not, get another book =))
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Re: Why is LDA/STA Absolute,X as fast ZeroPage,X?
It's the machine language book by Butterfield...so I must have missed something there on the chart. LOL...thanks man
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Re: Why is LDA/STA Absolute,X as fast ZeroPage,X?
The 65xx can add the X-register to the low-byte of the address while the high-byte is fetched over the bus.
If then there is a carry with LDA, the CPU will first do a read access from a wrong address (i.e. with the uncorrected high-byte), say "oops", and then re-do the fetch with the correct address.
That's the reason a STA ABS,X always takes 5 cycles: the CPU can't afford to trash memory. For this reason, the first access 'attempt' is converted to a read access (to the possibly wrong address [1]) whose result is discarded, and then the second access is the write to the correct address.
These spurios read accesses can make problems with read sensitive I/O registers, so you have been warned.
[1]: on CMOS variants, the address behind the current instruction is read instead
If then there is a carry with LDA, the CPU will first do a read access from a wrong address (i.e. with the uncorrected high-byte), say "oops", and then re-do the fetch with the correct address.
That's the reason a STA ABS,X always takes 5 cycles: the CPU can't afford to trash memory. For this reason, the first access 'attempt' is converted to a read access (to the possibly wrong address [1]) whose result is discarded, and then the second access is the write to the correct address.
These spurios read accesses can make problems with read sensitive I/O registers, so you have been warned.
[1]: on CMOS variants, the address behind the current instruction is read instead
Re: Why is LDA/STA Absolute,X as fast ZeroPage,X?
I've reached a point where I'm getting really interested in what's going on at the Phase 1 and Phase 2 level. I appreciate the warning about the read sensitive I/O registers going hanky.
Got some more reading to do - thanks man
Got some more reading to do - thanks man
Learning all the time...
Re: Why is LDA/STA Absolute,X as fast ZeroPage,X?
to examine that kind of details, the simulator from visual6502.org can be really helpful (as it shows every cycle with everything you ever wanted to know - and more )
I'm just a Software Guy who has no Idea how the Hardware works. Don't listen to me.
Re: Why is LDA/STA Absolute,X as fast ZeroPage,X?
Hey thanks for the link man!
Learning all the time...