6561 Die Shot Reversing Explorations

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lance.ewing
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Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Dec 02, 2017 11:27 am

I'm now going to take a look at the Screen Origin Y (CR1) vs Vertical Counter comparator. The following picture shows where this comparator is on the die shot, highlighted in red:

screen_origin_y_comparator_highlighted.jpg

It's been a while since I've shown a close up of the section of die shot being discussed in a post, so I thought I might do that this time since this comparator has quite a tidy layout. The picture below shows a close up of the area highlighted in red in the previous image:

screen_origin_y_comparator_die_shot.jpg

At the top of the image above, you'll see nine polysilicon lines coming in to the image from the area of the die shot above this section. The first line on the left is the interlaced bit and we can ignore this for the rest of this post since it is simply passing through. The other eight lines are carrying the eight bit values from CR1, i.e. the Screen Origin Y control register, which is immediately above this comparator.

At the bottom of the image, you'll see eight polysilicon lines coming in to the image from the area of the die shot below this section. These are bits 1-8 of the vertical counter (note that bit 0 is not used by this comparator). Most of the rest of the image is the comparator itself, being made up of eight identical 1-bit comparator cells.

In the image below, I have zoomed in closer on the top three of those 1-bit cells and have drawn around the diffusion (in green), polysilicon (in red), buried contacts (in blue), metal to diffusion contacts (in white), and metal to polysilicon contacts (in grey).

screen_origin_y_comparator_labelled.jpg

The following diagram shows the logic for the top one of these cells:

screen_origin_y_comparator_single_cell.png
screen_origin_y_comparator_single_cell.png (1.86 KiB) Viewed 250 times

The other two cells are identical, in fact all eight of the cells have identical logic. The outputs of all eight become inputs to an 8-input NOR gate, as shown in the following completed logisim diagram for the comparator:

screen_origin_y_comparator_logisim.png
screen_origin_y_comparator_logisim.png (10.61 KiB) Viewed 250 times

The output of the large NOR gate I have called SY COMPARE. This comparator compares the bits in CR1 (i.e. the Screen Origin Y value) with bits 1-8 of the vertical counter. SY COMPARE will go high when the two 8-bit values are equal and will be low in all other cases. I have included bit 0 of the vertical counter (VC0) in the diagram, and have it not connected to anything else in this diagram, to show that bit 0 of the vertical counter is not included in this comparison. This is why the Screen Origin Y value has a two line granularity. Incrementing the value in CR1 will cause the video matrix to move down two lines because this comparator only matches even vertical line values.

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Re: 6561 Die Shot Reversing Explorations

Postby norm8332 » Sat Dec 02, 2017 5:10 pm

Still following this..(I love this stuff) :D I wonder if Kakemoms got that 6560 yet? Its been awhile since it was sent..long journey though.

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Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Dec 02, 2017 5:23 pm

The Screen Origin X / Horizontal Counter comparator is to the left of the Screen Origin Y / Vertical Counter comparator. It is highlighted with a pink box in the following diagram of the die shot:

screen_origin_x_comparator_highlighted.jpg

This comparator is of an almost identical design to the comparator discussed in the previous post. Apart from having one cell less (i.e. seven instead of eight), the layout of this comparator is basically a mirror image of the previous comparator's layout. I was actually able to copy the polygons I traced around the previous comparator, flip them horizontally, and then move them in to place on top of this comparator. The polygons matched perfectly.

The following diagram shows what I created in logisim for this comparator:

screen_origin_x_comparator_logisim.png
screen_origin_x_comparator_logisim.png (9.13 KiB) Viewed 238 times

I've tried to keep things roughly as they are arranged in the die shot. So since the layout of this comparator is flipped horizontally when compared with the previous comparator, you'll notice that the outputs from the seven cells come out on the right side rather than the left.

This comparator compares the Screen Origin X value (SX0-SX6, i.e. the lower 7 bits of CR0) with bits 0 to 6 of the Horizontal Counter (HC0-HC6 in the diagram above). This time I've shown the counter bit values coming in from the left because that is the direction that these inputs come in from on the die shot. The large NOR gate has only seven inputs in this case. The output of the large NOR gate (which is also the output of the comparator as a whole) I've called SX COMPARE. It will go high when the Horizontal Counter value matches the Screen Origin X value.

As we know, the granularity of the Screen Origin X values is 4 pixels, e.g. increment this value by 1 and the video matrix moves 4 pixels to the right. In the case of this comparator, that is due to the fact that the pixel clock is four times the frequency of the clock signal that increments the Horizontal Counter. We've previously mentioned when discussing the Horizontal Counter that it counts up in VIC 20 machine cycles (i.e. at the rate of the output clock from the 6561). There are 71 cycles per line for the PAL 6561 chip, and four pixels for each of those cycles. The Horizontal Counter counts from 0 to 70 then resets back to 0. Since the Screen Origin X value is being compared directly with the Horizontal Counter value, the video matrix can only move in 4-pixel increments.

I thought that I'd now show a diagram with the two comparators side by side as they are on the die shot. The Interlace line does go down between the two as shown but has no effect and is just passing through:

screen_origin_comparators_logisim.png

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Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Dec 02, 2017 5:50 pm

norm8332 wrote:Still following this..(I love this stuff) :D I wonder if Kakemoms got that 6560 yet? Its been awhile since it was sent..long journey though.

Yeah, I was wondering the same thing a few days ago. Looking forward to seeing the results.

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Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Tue Dec 05, 2017 7:32 am

Hi,

Well, the chip is in a mixure of nitric acid and sulphuric acid at 120C right now. The Epoxy is peeling away, but it is soooo slow. After one hour its not visibly thinner, but I guess it probably is. The large chip generates alot of black smear that solidifies instantly if one lifts it out of the hot beaker.

Anyway, I will take pictures once I get in to the actual chip. It may take some days to get there as its very slow and I have to babysit the hot acid. I will post the pictures here once they are ready.

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Re: 6561 Die Shot Reversing Explorations

Postby norm8332 » Tue Dec 05, 2017 8:08 am

Glad to see it got there OK. Thanks for taking the time to try this. I still have another chip, I still might try rosin for the epoxy removal at a later date. The chip could probably be cut down a bit to reduce the amount of epoxy.

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Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Sat Dec 09, 2017 11:39 am

I had to go travel, so I couldn't finish the etch. I got about half way in 3 hours and will finish when I get back (in around a week). I don't think cutting is going to speed it up, and grinding isn't wise when you don't know were to stop... The safe way is nitric+sulphuric, and that should also leave most of the metal.

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Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Dec 16, 2017 10:32 am

I can't wait to see it. Well I can wait, but you know what I mean :D

I have noticed a number of redundant sections of logic in the 6561 die shot, in fact I've spent time reversing a few sections only to find that they are not connected to anything. So it will be interesting to see if those same sections are not used in the 6560 or whether they instead do have a use that was not required in the 6561.

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Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Dec 16, 2017 12:15 pm

The next part of the die shot that I'm going to look at is the bit that works out whether the current horizontal counter and vertical counter values are within the video matrix. The image below shows where in the die shot this logic lives, highlighted with a pink box:

within_video_matrix_highlighted.jpg

This time I've drawn a pink line down the middle of the box to separate two parts of the logic, which I will discuss later on.

The following image shows the logisim circuit that I created for this part of the die shot:

within_video_matrix_logic_6.png

I have been holding back posting this information for a while because I'm still not certain how it works. I think I know what it is doing, but this is another case where my simulation doesn't match my expectations (see the Edit comment below, as I believe I now know more about how it works than I did when originally posted). Essentially what this does is use various input signals to determine whether the current X/Y position is within the video matrix area, i.e. it works out whether the X and Y values (i.e. the horizontal counter value and vertical counter value) are within the currently defined video matrix area. All of the inputs shown are outputs that we have seen in previous diagrams. The SX COMPARE and SY COMPARE are the most recent that we have seen. They go high when the X and Y values match the Screen X origin and Screen Y origin. They are the signals that work together to determine when entry into the video matrix occurs. Exit out of the video matrix is controlled by the other signals.

For a particular frame, the SY COMPARE signal will go high first to say that the Screen Y origin has been reached. Then the SX COMPARE signal goes high for one cycle to say that the Screen X origin has been reached. The current X/Y position is within the video matrix. For this line, it will exit the video matrix on one of two conditions: Either the HORIZ CELL CNTR LAST VALUE goes high (i.e. the Horizontal Cell Counter has reached its final value), or the START OF NEW LINE signal goes low (i.e. we've reached the end of a line and are now starting a new line).

The exit of the video matrix in the Y direction happens when either the VERT CELL CNTR LAST VALUE goes high or the LAST LINE goes high.

This is where I add a few caveats. Some of what I've said above is almost certainly wrong. I know this because it doesn't make sense to me. For example, it doesn't make sense that the exit out of the video matrix in the Y direction happens when LAST LINE or VERT CELL CNTR LAST VALUE goes high. I think it must instead be on the negative edge, but I haven't been able to work out how that works at the silicon level.

If you look back at the die shot diagram, you'll remember that I mentioned I'd drawn a pink line through the middle of the box. Everything I've mentioned so far is the logic on the left half of the box. On the right side is some logic to generate the signals that control when the horizontal cell counter increments and when the video matrix counter increments. The signal generated by this logic also goes way down to the pixel output logic and a few other as yet undetermined sections. Initially I was unable to successfully simulate this using logisim, but after I realised I'd missed out an inverter, I now believe I understand how this works. I have traced the output of this section and I am certain that it enables increments of the horizontal cell counter. It also enables increments of the video matrix counter. When I reversed the logic for the previous counters, such as the horizontal counter, the video counter, and the cell depth counter, I had believed that these counters count on a certain edge of this increment input, but now I believe that this is actually an increment enable input and that instead if the increment input is enabled then the normal clock cycles will increment the counter. This is how I believe that this WITHIN MATRIX' output is used. If it is low, then the horizontal cell counter and video matrix counter will increment on each clock cycle. Those counters will not increment if the WITHIN MATRIX' output is high.

The NON MATRIX LINE output is the line that connects to the NON MATRIX LINE input shown in the CDC RESET logic diagram.

The BUS AVAILABLE output at the bottom goes down to the bus available output pad, which is not connected to a pin in the case of the VIC 20's 6561 since it is an option and isn't the option associated with the 6561-101 version of the chip. The datasheet makes it clear that this pin would go low just before the VIC chip starts using the address bus if it happened to be a 6561-301 version of the chip.

Edit: I have corrected a few things in the above text and diagrams from the originally posted version since I realised that I'd missed out an inverter from the lower right output :oops:. This completely changes things. I had previously called this output NEXT CELL' but now I realise that it stays low whenever the X/Y position is within the video matrix, so I have called it WITHIN MATRIX'. Rather than being a pulse generator, that lower left sequence of inverters is simply a delay. It doesn't commence incrementing the horizontal cell counter and video matrix counter until two cycles after the X and Y position are within the video matrix. Not sure why yet.

Edit 2: I have updated the logisim diagram and text to reflect that I now know for certain what the output I had previous called UNKNOWN is. In the originally posted version, I said that it appeared to be associated with the BUS AVAILABLE output pad but wasn't sure whether it directly reflected that or not. Now I know that it is the BUS AVAILABLE signal. I also realised that I previously had the signal coming out on the wrong side of the inverter :oops: and so have corrected this. BUS AVAILABLE goes LOW just before WITHIN MATRIX' goes LOW.
Last edited by lance.ewing on Sun Jan 14, 2018 4:54 pm, edited 2 times in total.

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Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Mon Dec 18, 2017 2:52 pm

Managed to get anoother two hours of boiling acid today. The IC case is very thin now (about 1mm), and my guess is another two hours will do the trick. Since the lab closes for xmas it will have to wait until after new year. The reason it takes so long may be my choice of mixing concentrated sulphuric and nitric acid. It should preserve most of the metal though so I am hoping for some good shots.

IMG_6096.JPG

The bubbling acid. The red color is dissolved NOx gas, which is not something you want in your house (basically because it will burn and disolve your lungs).

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Re: 6561 Die Shot Reversing Explorations

Postby cbmeeks » Tue Dec 19, 2017 9:58 am

Sorry if I'm asking the obvious here (haven't read all five pages) but, is the purpose of this to provide 100% accurate schematics and, perhaps, a modern replacement like FPGA and/or TTL logic?

The same thing was done with the ULA in the ZX Spectrum and the thought of this level of detail for the 6561 is very exciting.

Of course, you would need to write a book too like Chris Smith did. :-D (I would purchase the first copy).
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Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Tue Dec 19, 2017 4:32 pm

We've obviously been thinking along the same lines. I have owned Chris Smith's book for the past couple of years, and coincidentally I was reading a couple of chapters from it earlier today. Brilliant book. I think we should definitely produce a comparable VIC chip book at the end of this.

I love what was done with the Harlequin ZX Spectrum clone.

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Re: 6561 Die Shot Reversing Explorations

Postby cbmeeks » Wed Dec 20, 2017 9:42 am

That's great to hear. I've read Chris Smith's book cover to cover at least 15 times.

Having a similar book detailing the 6561 and perhaps creating an open source design for a modern VIC-20 would be an absolute joy. Something that is cycle accurate but uses modern parts (and isn't 100% in an FPGA).
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Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Fri Dec 22, 2017 2:25 pm

I managed to get another hour of acid etch, and now the chip is 3/4 free of epoxy. For some reason the last 1/4th seemed to be stuck. I hope its not fried epoxy, but I'll eventually find out when the lab opens again.

Do you know why the IC stopped working?

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Re: 6561 Die Shot Reversing Explorations

Postby norm8332 » Fri Dec 22, 2017 2:42 pm

That chip did not smoke. It died gradually. When is was used it actually would work for a some minutes then freeze/ go to black. Then the next time it would work for a shorter time until it eventually stopped altogether with just a black screen. I assumed it was a wire disconnect or microscopic delamination because of repeated thermal cycling.


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