lance.ewing wrote:I still haven't completely worked out what is going on in the vertical counter reset logic. What I have so far isn't making sense compared with what I think I know about how it should work.
I have decided to present the diagram that I have at the moment for the vertical counter reset logic, even though it still doesn't make sense to me. I have a feeling that I have reversed part of it incorrectly, but I'll post what I have and will come back to this post at a later point when and if I discover what it is that I've got wrong. I want to post it now because I've already moved on into other parts of the chip (like the cell depth counter and horizontal cell counter) and want to start posting about what I've discovered in those areas. I didn't want to leave this vertical counter reset logic out of sequence though.
So below we have what I'll call the preliminary version of the diagram. This is for the area that has the purple box around it in the most recent die shot picture that I posted:
Towards the top left we have a 3-input NOR gate. The first input will be high whenever the vertical counter has a value of 311. The second input will never turn on because the Y decoder says that this turns on whenever the vertical counter is at 312 and the interlace bit is both ON and OFF, which is obviously an impossible scenario (probably done like this to disable the interlace logic). The third input I have called FORCE VCNT.RESET. It will also never turn on because the 6561 in the VIC 20 doesn't use the external reset option. But let's say that the external reset bonding pad was connected to the option pin, then this FORCE VCNT.RESET is a way to reset the vertical counter at any point, regardless of what value it is currently at. You will also notice that it is connected to a pull down transistor that will pull down the output of that small NOR gate slightly left of middle at the top. Normally that smaller NOR gate would have an output of low if X=0 or X=35, but if the reset is being forced, then it pulls that output low and therefore also doesn't care what the horizontal counter value is currently at.
So given that two of the inputs to that large 3-input NOR gate will never go high in the 6561 used by the PAL VIC 20, then it means that the output of that NOR gate will only go low when Y=311. This in turn means that the output I've shown labelled as LAST LINE will turn on when Y=311. This output links to quite a number of other areas in the die shot.
The two outputs in the bottom right hand corner are the two inputs shown in the bottom left corner of the vertical counter diagram that I posted previously. On that previous diagram, I labelled those inputs X=0 and X!=0,35. To be more precise, that X!=0,35 line goes high only when the LAST LINE is low, i.e. only when it is not the last line and X isn't equal to 0 or 35.
For the input X=0 on the vertical counter diagram, it relates to the output of the NOR gate in the bottom right. The net effect of this NOR gate is that the output goes high whenever X=0 but only as long as it isn't the LAST LINE, i.e. only as long as Y != 311. This output going high is what makes the vertical counter increment by one.
The F1 output I've labelled as F1 but actually it will only match F1 as long as VCNT.RESET isn't high.
And that brings us on to VCNT.RESET, which is the bit that confuses me. This output connects to the RESET input shown in the vertical counter diagram I posted. We know that the vertical counter isn't going to count any higher than 311 as a consequence of that logic described above. We also know that there are 312 lines with the PAL VIC chip, and all 312 lines are full 71 cycle lines. To be certain of this, I spent some time with my Picoscope doing various measurements and I'm pretty certain the last line is a full 71 cycle line. The reason I started thinking about this is because of that X=35 input. I assumed it was completely redundant, and a part of me still thinks it is. But the logic I have reversed seems to suggest that the vertical counter would reset when X=35 on the last line. This is what doesn't make sense to me, and is why I'm sure I've got something wrong. Perhaps it would make sense for an interlaced mode but for the 6561, I must be missing something that has disabled this.
Anyway, if we look at what the diagram shows, it says that VCNT.RESET will go high when it is the LAST LINE and either X=0 or X=35. I don't think that it will go high at the start of line 311 because of the timing. X will have already moved on to a value of 1 by the time Y=311 is matched and has gone through that 3-input NOR gate. You'll notice that there are two pass transistors between the Y=311 input and the NOR gate that calculates the VCNT.RESET value, where one of the pass transistors is turned on with F1 and the other with F2. The X=0 input has no such delays, and since it is X=0 that increments the vertical counter to Y=311, then I would expect that X will have moved on to the next value, i.e. 1, by the time the VCNT.RESET value is calculated. If this wasn't the case then we'd only have 311 lines, which obviously we don't.
The only bit that doesn't make sense is that X=35 input. I've simulated this and VCNT.RESET goes high when X=35 on the LAST LINE. It doesn't make sense and clearly I have to check things over a few more times and try to work out why it doesn't reset at that point on the last line.
I'm going to leave it like that for now and will revisit this post to make amendments when I solve this mystery.