lance.ewing wrote:...the X=35 is probably completely redundant. It is used in one other place, which we're going to look at next. And in the process we'll also see what triggers the vertical counter RESET.
...but not quite yet. I still haven't completely worked out what is going on in the vertical counter reset logic. What I have so far isn't making sense compared with what I think I know about how it should work. So I'll let that one simmer for a while while I look at other areas nearby, the first of those being the horizontal counter.
Over the weekend, I traced around the biggest bit of diffusion I have traced around to date. The completed polygon path has 1230 nodes. Not certain exactly how long I was clicking away in Inkscape for that one, but it must have been over an hour, maybe close to two. That was all part of reversing the horizontal counter, which happened to be connected to a rather large bit of diffusion that was involved in various other non-related things. Diffusion areas connected to VSS or VDD quite often end up being connected to many different logic gates and therefore the polygons get quite large when tracing them.
The horizontal counter is located in the area of the die shot shown highlighted below with the light blue (I will at some point produce a black and white labelled functional block diagram):
You will notice that I highlighted an additional three areas in this diagram. I thought I would include them since I've already worked out what they do. The red is the horizontal counter reset logic, the purple the vertical counter reset logic, and the darker green the logic for controlling when to latch the light pen latches. The topic of this post is the horizontal counter though. The logisim diagram below is the end result of reversing the horizontal counter:
No surprises that it looks very similar to the vertical counter. The logic gate design for the individual bits is exactly the same as for the vertical counter, and I wouldn't be surprised that the same design will be used for the other counters when I eventually locate them. The horizontal counter is a bit simpler than the vertical counter. It has only the 8 bits, and there isn't a separate input to trigger the increment by one. Instead this is triggered simply by clocking the circuit with the phase 1 and phase 2 clock signals. The version of the logisim diagram above is as the circuit actually is on the die shot. So for the reset input, it shows the transistors that either pull up or pull down for each bit when the reset goes high. The diagram in my previous post of the vertical counter didn't show these transistors because as I mentioned in that post, I had to create a custom component to simulate the behaviour of that reset line. I did the same thing for the horizontal counter, and confirmed that it counts up through the bits as I toggle the F1 clock input, but I also produced a version that shows the actual circuit with the reset pull up and pull down transistors, which is what I'm showing above.
The outputs at the top of the diagram are obviously what goes on as inputs in to the X decoder. They also go up to the horizontal light pen latch and to a comparator that compares the counter value with the screen origin X value.
Although not shown in this diagram (since it is part of the horizontal reset logic), I can tell you that the reset goes high when either the value 70 is matched by the X decoder, or when the external reset pin is used. The external reset pin is one of the three options that the 6561 had. Obviously in the VIC 20 the option used is the light pen input, but the die shot still has the bonding pads for the other two options, and all the logic for implementing those options. The "option" is basically just choosing what bonding pad to connect the pin to. But given that in the VIC 20 the 6561 doesn't support the external reset, then the only time that the horizontal counter resets is when it gets to 70. So now we know what that 70 output from the X decoder controls, which probably isn't a surprise to anyone.
No idea why this is an 8-bit counter when all it needs is seven bits (...unless their design was putting things in place for the 6562/3?). The 8th bit seems completely redundant for the 6561. It is present, and it goes as an input to the X decoder, but is basically ignored by the X decoder since there are no horizontal counter values above 70. The 8th bit does not go anywhere else, i.e. it is not latched by the light pen latch and it is not used by the comparator that compares the horizontal counter with the screen origin X value in CR0.
It is worth noting that those F1 (phase 1) and F2 (phase 2) inputs are at the frequency of the 6561's output clock pins and that this counter counts up with each cycle of that clock, i.e. the same as what drives the rest of the VIC 20.
One other thing to mention is that pull down at the left end of the F1 and F2 lines. It seems that when F2 is high, this transistor pulls down the F1 line, which is kind of interesting. They're already meant to be non-overlapping signals, so not sure why that is needed. I did notice, however, that a capacitor is connected to the pass transistor that controls F1's access through to the F1 line shown in the diagram. When F2 is high, this capacitor appears to get charged (as long as horizontal reset is not high), then when F2 goes low, this capacitor keeps the pass transistor active for a while to let F1 through. I don't understand the reason for this, but I'm sure it must be important to the design of the chip. I'm thinking mainly at a logical level, so that's why I've simplified the diagram to show simply F1 as an input.