lance.ewing wrote:Kakemoms wrote:Interesting. Have you thought about making a Verilog or vhdl file, and simulate it there? Lattice Diamond is free and includes a simulator (Active vhdl).
I'll certainly take a look at Lattice Diamond. Currently I don't know Verilog or VHDL but they're on my list to learn. One of the nice things about Logisim Evolution is that it can generate both Verilog and VDHL (as long as you stick to the components that it supports that for). My plan was to get the simulation working first in Logisim Evolution and then generate the Verilog and/or VHDL as a starting point for moving it into another tool, perhaps something like Lattice Diamond. I'd hopefully learn a bit of VHDL and Verilog by looking at what is generated by Logisim Evolution.
Ok. You got some late evenings there! I like Verilog for its simplicity in syntax, for its complicated statements, its hellish seemingly unrelated cross-conneted bugs and wide availability. But you can probably say the same for VHDL..
As for 6502, one guy used the 6502 netlist from visual6502.org and made a working core from that! I wouldn't suggest you do anything like it...