6561 Die Shot Reversing Explorations

Modding and Technical Issues

Moderator: Moderators

User avatar
Kakemoms
Vic 20 Nerd
Posts: 542
Joined: Sun Feb 15, 2015 8:45 am

Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Sat Jan 27, 2018 11:38 pm

lance.ewing wrote:
Kakemoms wrote:Interesting. Have you thought about making a Verilog or vhdl file, and simulate it there? Lattice Diamond is free and includes a simulator (Active vhdl).

I'll certainly take a look at Lattice Diamond. Currently I don't know Verilog or VHDL but they're on my list to learn. One of the nice things about Logisim Evolution is that it can generate both Verilog and VDHL (as long as you stick to the components that it supports that for). My plan was to get the simulation working first in Logisim Evolution and then generate the Verilog and/or VHDL as a starting point for moving it into another tool, perhaps something like Lattice Diamond. I'd hopefully learn a bit of VHDL and Verilog by looking at what is generated by Logisim Evolution.


Ok. You got some late evenings there! I like Verilog for its simplicity in syntax, for its complicated statements, its hellish seemingly unrelated cross-conneted bugs and wide availability. But you can probably say the same for VHDL..

As for 6502, one guy used the 6502 netlist from visual6502.org and made a working core from that! I wouldn't suggest you do anything like it...

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sun Jan 28, 2018 4:15 pm

Kakemoms wrote:Ok. You got some late evenings there! I like Verilog for its simplicity in syntax, for its complicated statements, its hellish seemingly unrelated cross-conneted bugs and wide availability. But you can probably say the same for VHDL.

Most evenings are late evenings, its just what I decide to focus on that seems to change each week. Over the past week, it has been this Logisim simulation. I'm finding that I am revisiting all my earlier diagrams and notes, and in a few cases spotting some mistakes, which is good. The simulation should certainly help to bring those to light. I am also creating what I hope are some easier to understand circuit diagrams. I can't seem to leave it alone if the layout doesn't look visually pleasing.

Logisim doesn't seems to like SR flip flops created by hand using NOR gates. They work in isolation, but as part of a larger circuit, they often get into an "Oscillation apparent" condition that causes Logisim to give up simulating. I can configure it so that it doesn't stop, or instead configure it to use random propagation delays, but I stopped to think about it and realised that I may as well swap any such SR flip flop circuits with the Logisim SR flip flop component, which doesn't appear to suffer from the same condition. It's actually making some of the circuits a lot easier to understand.

Kakemoms wrote:As for 6502, one guy used the 6502 netlist from visual6502.org and made a working core from that! I wouldn't suggest you do anything like it...

Hopefully we'll get there one day with the 6561 and 6560. On a related note, I discovered that last year someone created a simulation of the 6502 in Logisim. Apparently it isn't an exact simulation, but it does execute 6502 machine code. Interesting.

https://www.youtube.com/watch?v=vhY6YTFdusM

There is a link to the Logisim circ file in the youtube comments. I've downloaded it for inspiration. Might even grab the appearance of the outside of the chip for my 6561 circuit. :D

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sun Jan 28, 2018 4:39 pm

As an example of how I've been revisiting some of these diagrams, and swapping sets of NOR gates with the functionally equivalent Logisim SR flip flop, take a look at this diagram of the "in the matrix" logic from this earlier post:

viewtopic.php?f=11&t=8733&start=60#p97851

The new diagram is as follows:

within_matrix_logic.png
within_matrix_logic.png (11.4 KiB) Viewed 178 times

Logisim Evolution forces me to use labels that can be used in the Verilog and VHDL generation. So I can no longer use spaces and apostrophes. To indicate that a signal is the inverse, I am now prefixing with i_ (not sure if there is a naming standard for that?). Anyway, you can see from the above that the introduction of the three Logisim SR flip flop components makes it easier to see what this circuit is doing. The top flip flop is set when the Y line that the matrix starts at is reached. The flip flop below that is set when the output of the top flip flop is HIGH and the X position of the video matrix left side is reached. So the output of this second flip flop is HIGH when the X/Y position is "in the matrix". The third flip flop is turned ON when this happens for the first time for a frame, i.e. on entry into the matrix at the top left corner. It stays on until after the last line of the video matrix. The output of that third flip flop is one of the three signals that controls enabling of the increment for the Cell Depth Counter, which makes sense when you think about it.

i_in_matrix: Is the inverse of the in_matrix signal and is used to enable the Horizontal Cell Counter and Video Matrix Counter.
i_mtrx_line: Is the inverse of the matrix_line signal and is used as part of the logic to enable the Cell Depth Counter.
bus_avail: Goes LOW about a cycle before the i_in_matrix signal goes LOW. It goes pretty much directly to the driver logic for the unused Bus Available bonding pad. This signal isn't used internally by the chip (or externally since the bonding pad is not connected to a pin).

The label names are still in a bit of flux. I'm learning more as I go along, and no doubt when I've got the simulation working, or while I'm trying to get it working, I'll discover better names for a few of them.

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Feb 03, 2018 12:38 pm

lance.ewing wrote:I'll certainly take a look at Lattice Diamond. Currently I don't know Verilog or VHDL but they're on my list to learn. One of the nice things about Logisim Evolution is that it can generate both Verilog and VDHL (as long as you stick to the components that it supports that for). My plan was to get the simulation working first in Logisim Evolution and then generate the Verilog and/or VHDL as a starting point for moving it into another tool, perhaps something like Lattice Diamond. I'd hopefully learn a bit of VHDL and Verilog by looking at what is generated by Logisim Evolution.

I might have to switch to Lattice Diamond sooner than I thought. I've been a bit depressed today because it seems that Logisim has a rather fundamental defect. The Vertical Counter value in my circuit seems to sometimes spontaneous increment by one. There is a pattern to it, but it certainly doesn't match what is happening with the inputs to the counter. When this happens, both the enable and increment inputs are LOW, which should mean it doesn't increment. I've put probes at all the relevant points and can see from the generated timing diagrams while it is running that the counter value changes without the enable or increment inputs going HIGH, both of which need to go high for the value to change. The counter is set to increment on the rising edge of the clock, but there's no edge at all. It's flat.

I've tried two different counter implementations as well, one being the built in Logisim counter, and the other being one I created from JK flip flops. They both work in isolation, but as part of the larger circuit, both implementations spontaneously increment when they shouldn't. The only thing I can think of to explain this is that there is a fundamental defect with the circuit propagation logic within Logisim itself. Even though it is open source, I really don't fancy trying to debug the Java code for Logisim to work out what is going on.

So I decided to register with Lattice earlier today and I'm now waiting until my account is activated enough to be able to download the Free version. Seems that I'm not able to do this initially, even though I've verified my email. I assume that someone has to manually verify it at their end as well.

User avatar
Kakemoms
Vic 20 Nerd
Posts: 542
Joined: Sun Feb 15, 2015 8:45 am

Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Sat Feb 03, 2018 3:56 pm

lance.ewing wrote:I might have to switch to Lattice Diamond sooner than I thought. I've been a bit depressed today because it seems that Logisim has a rather fundamental defect. The Vertical Counter value in my circuit seems to sometimes spontaneous increment by one. There is a pattern to it, but it certainly doesn't match what is happening with the inputs to the counter. When this happens, both the enable and increment inputs are LOW, which should mean it doesn't increment. I've put probes at all the relevant points and can see from the generated timing diagrams while it is running that the counter value changes without the enable or increment inputs going HIGH, both of which need to go high for the value to change. The counter is set to increment on the rising edge of the clock, but there's no edge at all. It's flat.

I've tried two different counter implementations as well, one being the built in Logisim counter, and the other being one I created from JK flip flops. They both work in isolation, but as part of the larger circuit, both implementations spontaneously increment when they shouldn't. The only thing I can think of to explain this is that there is a fundamental defect with the circuit propagation logic within Logisim itself. Even though it is open source, I really don't fancy trying to debug the Java code for Logisim to work out what is going on.

So I decided to register with Lattice earlier today and I'm now waiting until my account is activated enough to be able to download the Free version. Seems that I'm not able to do this initially, even though I've verified my email. I assume that someone has to manually verify it at their end as well.


Ah. Too bad! But you'll find that logic statements are a lot faster to define in Verilog, and you can even get the diagram plotted out quite nicely. It takes some time to get hold of the Lattice Diamond package, mostly because it has so many options. I would recommend to stick to the Lattice compiler until you have some really large code (the Symplify PRO compiler gives you faster and smaller code, but also less than understandable errors). The simulator is a really nice thing to use once you defined a state machine around your model.

My general advice for Verilog is to change, compile, test, change, compile, test.. If you get some strange results at some point, its much easier to go back than to actually understand what is wrong.

I have registered many free licenses, and it usually only takes a few minutes to get the license file.

Happy coding! :roll:

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sun Feb 04, 2018 9:55 am

Kakemoms wrote:I have registered many free licenses, and it usually only takes a few minutes to get the license file.

I thought I was up and running, but seems I've run into a license issue. I downloaded the install file, installed it, requested the Free license, then started working my way through the tutorial. First issue I encountered was that I didn't have the Free license for the device they said to use in the tutorial, so I found that link on their site, requested it and installed it. The second issue is that the Aldec Active HDL simulator will not launch. The error I get is as follows:

Code: Select all

(FLEXlm error = -5) No such feature exists.

Please run the License Information of the Help menu to verify Aldec license environment settings or define new license.
For ordering information contact sales@aldec.com.

I checked over the features that Lattice Diamond comes with and apparently this is meant to be included. So I opened the license.dat file that they emailed me and it contains the following text:

Code: Select all

Feature has expired.
Feature:       ACTIVEHDL_LATTICE_LIC_GEN_V2
Expire date:   31-jan-2018

Apparently it expired a few days ago, even though it was today that I did the install and requested the license file. The file they sent me already has this expiry message in it, so I assume there is something wrong at their end with the license file generation and its a message meant for them to say their license generation for that feature has expired. I guess I should email them about this.

Hopefully I can continue with the remainder of the tutorial, but it would be nice to have the simulator.

User avatar
Kakemoms
Vic 20 Nerd
Posts: 542
Joined: Sun Feb 15, 2015 8:45 am

Re: 6561 Die Shot Reversing Explorations

Postby Kakemoms » Tue Feb 06, 2018 2:46 am

Once you start the simulator, it will continue to run. So if you launch the simulator again from Lattice Diamond, you will get two instances of the simulator. The second instance will not have a license and you will get that error..

Or maybe there is something with the installation (if you never launched the simulator before), but I have it running on three computers without any problem..

Note that you can change the code inside the simulator environment, compile it and run. Its much faster than actually going back and forth between the two programs.

PS: The license files are only active for one year, and needs to be renewed after that.

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Feb 10, 2018 3:12 am

Kakemoms wrote:Once you start the simulator, it will continue to run. So if you launch the simulator again from Lattice Diamond, you will get two instances of the simulator. The second instance will not have a license and you will get that error..

Or maybe there is something with the installation (if you never launched the simulator before), but I have it running on three computers without any problem..

I did email Lattice and they confirmed it was an issue at they end with the license generation. They resolved it after a day or so and sent me a new licence and said that requesting one online should now also work.

Kakemoms wrote:Note that you can change the code inside the simulator environment, compile it and run. Its much faster than actually going back and forth between the two programs.

PS: The license files are only active for one year, and needs to be renewed after that.

Thanks for the tips.

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Feb 10, 2018 3:49 am

While I'm getting up to speed with Lattice Diamond, I thought I'd post a few more alternative diagrams for sections of the die shot that I've previously covered, like I did a few posts ago with the "in matrix" logic. When I was working on the full simulation in Logisim (before encountering the seemingly insurmountable issue), I created the circuit below for the Y Decoder. Compare this to the original diagram from page 1 of this topic:

viewtopic.php?f=11&t=8733

The main differences are that the original diagram showed the pull down transistors and the pull ups for the big NOR gates. The diagram below is now showing these as NOR gates, and the SR flip flops are also shown. It probably makes it a bit clearer what is going on.

y_decoder.png

Click on it to get a closer view (vc=vertical counter, i_vc=inverse of vertical counter). Like I did in the original diagram, I've included the redundant parts. So there is a NOR gate sitting there without any inputs or outputs. I am assuming that it had a use in the 6560 but was disconnected for the 6561. And I've got those four lines on the far left that are also completely redundant (as is the bottom most NOR gate as well, since it requires the interlace to be both ON and OFF at the same time, and besides, the 6561 never goes beyond y=311).

You'll notice that I used a MUX where in the previous diagram I had a pass transistor. This was part of trying to stick to components that would generate Verilog or VHDL. The transistor was one component that wasn't supported, nor was the controlled buffer, which I could also have used in place of a pass transistor.

User avatar
lance.ewing
Vic 20 Afficionado
Posts: 311
Joined: Sat Nov 10, 2012 3:19 pm
Website: https://sites.google.com/site/mos6561vic/
Location: Berkshire, UK

Re: 6561 Die Shot Reversing Explorations

Postby lance.ewing » Sat Feb 10, 2018 4:05 am

lance.ewing wrote:I will be building a logisim diagram for the X decoder, but thought I'd do it all in one go this time. I seem to be progressing through this one a bit quicker.

Despite making the above comment a few months back, I've realised now that I never did produce the Logisim diagram for the X decoder, so here it is from the recent Logisim Evolution simulation I was working on:

x_decoder.png


Return to “Hardware and Tech”

Who is online

Users browsing this forum: No registered users and 2 guests