SuperCPU for the Vic-20

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Kakemoms
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SuperCPU for the Vic-20

Post by Kakemoms »

After many long hours and alot of Verilog coding, I have finally made a soft core addon to the Vic-20.

What is it? Well, its a SuperCPU for the Vic-20. It currently runs at 22MHz and has a 65C02 core made by BigEd and Dave[hoglet] (an extension of Arlets 6502 core).
Vic-20 screen grabbed
Vic-20 screen grabbed
My Vic-20 screen grabbed by a videograbber. Background is Lattice Diamond programming suite for Verilog. The Vic-20 copies a buffer to the screen that has been modified by the 65C02 program running in the prototype expansion.

The 65C02 is accessible from the Vic-20 side as expanded memory. I currently use the internal memory of the MachXO3L, but I can add DRAM and a number of other things later.

Now, if someone wants one of these I will have to make a small test run of PCB cards. The MachXO3L is tiny and it only requires a few other ICS. So the card will be a small one. I won't add SDCard, lots of mem or IO interfaces for such a test, so its basically a fast CPU addon for your Vic-20 that plugs into the expansion port.

You can flag your interest here - I will make it as cheap as possible.
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Schlowski
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Re: SuperCPU for the Vic-20

Post by Schlowski »

An accelerator card for the VIC-20? I'm definately interested in this!

Could you give some more insights about how to use the 65C02 from the VIC? How to start programs on it etc. I'm not sure if I understand
The 65C02 is accessible from the Vic-20 side as expanded memory.
Is the 65C02 running parallel to the in-built 6502 of the VIC and just map it's memory to the VIC? Has it access to the VIC video chip/onboard RAM? I don't think so, right? So to show something the 65C02 has produced the 6502 has to copy it to the screen RAM for example?
Kakemoms
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Re: SuperCPU for the Vic-20

Post by Kakemoms »

Well, we have a choice of options for how to implement it. Currently it runs on a MachXO3L-6900 which has a maximum 26KBytes of internal memory. But it would be easy enough to just use the new MachXO3L-9800 which has 54KBytes internally (but is still in pre-production, so it would take a little longer to get things ready). For the first run I therefore want to use the XO3L-6900 to get things going.

Anyway, currently it can be seen as a 16Kbyte memory expansion from the Vic-20 side. The lower 8K is internal on the Vic-20 and the lower 8K for the 65C02 is therefore not accessible. I could move this up so that it looks like a 24KByte expansion from the Vic-20, but then the addresses (on the Vic-20 and 65C02) would be different. So for now its placed at the lower 24K (e.g. from $0000-$6000) and only addresses above $2000 are visible from the Vic-20 side.

Once its started you can put programs in this memory area and you put 65C02 start address at $3FFC (LSB) and $3FFD (MSB). Then access address $3FFF to start the 65C02 (LDA/STA or PEEK from basic). Another access to $3FFF would stop the 65C02 (put it into reset mode at time being). I will move the $3FFC, $3FFD and $3FFF addresses to another area before this ships; I just used these for convenience.

Once the 65C02 starts, it can use the whole $0000-$6000 expansion area, but anything below $2000 is invisible from the Vic-20 side. Stack is $100-$1FF as usual (and so on).

To get things onto the Vic-20 screen you need to use the internal 6502 of the Vic-20 to copy any data from $2000-$6000 and onto the screen (as the Vic-I chip can't see this area). Since both processors run at the same time (without interference) there is no speed penalty for accessing the $2000-$6000 range while the 65C02 is running.

I am assuming the cost is going to be around 60-70Euro/pc + shipping for this prototype run. It is probably going to be around 10 pcs as it will be mounted manually.

Anyway, you are first in the queue.
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eslapion
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Re: SuperCPU for the Vic-20

Post by eslapion »

Dual port SRAM allows 2 different CPUs to access the same memory.

It would be inadvisable to have them share the 1st 1k but the 4k of RAM from $1000-$1FFF could be shared by 2 different CPUs and the W65C02 can run up to 20MHz.
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Schlowski
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Re: SuperCPU for the Vic-20

Post by Schlowski »

Thanks for your explanation, very interesting. This will be very fun to experiment with!
as it will be mounted manually.
I hope this means mounted by you as I am definately not able to solder...
Kakemoms
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Re: SuperCPU for the Vic-20

Post by Kakemoms »

Schlowski wrote:Thanks for your explanation, very interesting. This will be very fun to experiment with!
as it will be mounted manually.
I hope this means mounted by you as I am definately not able to solder...
Yes I do the soldering.
Kakemoms
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Re: SuperCPU for the Vic-20

Post by Kakemoms »

eslapion wrote:Dual port SRAM allows 2 different CPUs to access the same memory.

It would be inadvisable to have them share the 1st 1k but the 4k of RAM from $1000-$1FFF could be shared by 2 different CPUs and the W65C02 can run up to 20MHz.
Dual-port SRAM is hugely expensive and would easily double the cost. The 65C02 core will be able to run faster than 22MHz, but it depends on a number of things. For a test run 22MHz is fine. Fortunately any improvement after the board has shipped can be upgraded via a simple USB cable to a PC.

Edit: Please also note that WDC has a commercial 6502 core for Lattice (that is faster), but for a small hobbyist project as this I haven't asked them about it.
groepaz
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Re: SuperCPU for the Vic-20

Post by groepaz »

WDC has a commercial 6502 core
unless you are planning to manufacture a couple million devices - dont even think about that one =P
I'm just a Software Guy who has no Idea how the Hardware works. Don't listen to me.
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eslapion
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Re: SuperCPU for the Vic-20

Post by eslapion »

Kakemoms wrote:Dual-port SRAM is hugely expensive and would easily double the cost.
I checked Digikey... for 10 Euros, the complete 4kBytes $1000-$1FFF can be dual port SRAM of 55ns.

See: CYDC128B16-55AXI

This is really 16 bit SRAM but you can just discard/NC the extra bits.
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Schlowski
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Re: SuperCPU for the Vic-20

Post by Schlowski »

Please excuse my ignorance, but changing RAm at $1000-$1FFF would mean soldering on the mainboard, right? As far as I understand the SuperCPU as implemented by Kakemons just sits in the expansion port, ready to run without modification of the mainboard - or did I miss something?
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Re: SuperCPU for the Vic-20

Post by Mike »

The internal RAM ($0000..$03FF, $1000..$1FFF) is not accessible from the expansion port, for the same reasons the VIC chip cannot access anything at the expansion port. The details of this have been discussed here in Denial often enough, no amount of wishful thinking is going to change that.

A SuperCPU of this design will only work by transferring data into the screen RAM using the 6502 on the mainboard. As for the memory accessible by the external CPU and that CPU's operation state, I gladly refer to a suggestion I made in 2011 in the thread 'Thinking of a SuperCPU VIC':
Mike wrote:I have an idea, which would require no internal mods: attach some higher clocked 65xx CPU to the expansion port, allow both CPUs to access the external RAM through some bus arbitration unit. The 6502 in the VIC-20 could see the external RAM as 8 times 8K blocks, mapped into, say, BLK3 over a banking register, and control the external CPU as being stopped, free-running (max-speed), 1 MHz synchronous, single-step, reset. Finally, you use the VIC-20 console as terminal, modifying the external RAM as necessary to feed the external CPU with data, and reading out the external RAM likewise, to display parts of it on the screen of the VIC-20 (text or bitmapped).

It is clear that this solution will not accelerate existing software, rather new software would need to be written for it.
... which easily could serve as blueprint for Kakemoms' project. The NMI/IRQ/reset vectors of the external CPU, for example, would then be accessible in the 8th bank of the external memory mapped into BLK3, visible at $7FFA .. $7FFF for the internal CPU. Stop the external CPU, init CPU vectors, init ZP, stack, RAM, 'release' the external CPU - and there you go. With whatever application one might conceive to run on the external CPU.

That being written, this post here does *not* constitute a further involvement of mine into this project.
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Schlowski
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Re: SuperCPU for the Vic-20

Post by Schlowski »

No wishful thinking on my side, I simply wanted to clarify that Eslapions 4K dual port SRAM would mean a mainboard modification which is not part of this project. Maybe my wording wasn't clear enough...
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Mike
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Re: SuperCPU for the Vic-20

Post by Mike »

Schlowski wrote:No wishful thinking on my side, I simply wanted to clarify that Eslapions 4K dual port SRAM would mean a mainboard modification which is not part of this project. Maybe my wording wasn't clear enough...
Hi, Björg - Du warst damit auch nicht gemeint. ;)
Kakemoms
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Re: SuperCPU for the Vic-20

Post by Kakemoms »

Well, dual or not. The Vic-20 has now access to 24KB of expansion memory in the unit, e.g. $2000-$8000. This is shared with the 65C02. The 65C02 also have 2KB of memory from $0000-$0800 which covers the stack, zeropage and some more. Of course, this area is not viewable from the Vic-20 which has its own internal memory for that area. Thus each processor has its own stack and zeropage.

As you have already understood, there is not much for the internal MOS 6502 to do when it has a sibling running at 25MHz (I increased the speed a little today without any penalty to signal slack). But to see things on the screen you have to have it in the internal memory. Thus, to see graphics from the 65C02, the internal MOS 6502 of the Vic-20 can be used to copy bytes into the internal memory (which the 6561 VIC chip sees and can display).

The way to do this is to have a loop that the internal MOS 6502 runs:

Code: Select all

$2000   LDA #yy
$2002   STA $xxxx
$2005   BCC $2000
This will store one byte each loop into the internal memory of the Vic-20 at location $xxxx. Value at $2001, address LSB at $2003 and MSB at $2004 can be easily modified by the 65C02 which runs 25 times faster. An even faster way is to unroll the loop so that it becomes:

Code: Select all

$2000   LDA #yy
$2002   STA $xxxx
$2005  LDA #vv
$2007   STA $uuuu
$200a   LDA #tt
$200c   STA $ssss
.
.
and so on
..
JMP $2000
Basically 6 cycles/byte (or 5 cycles if in zeropage). For a 190x160 bitmap this will consume (3800bytes*6) + 3 cycles = 22803 cycles and 19KB of memory as buffer.

Later, I will add more RAM to the 65C02, so large buffers shouldn't be a problem. In fact I will probably put down traces and space for that on the first layout.
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eslapion
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Re: SuperCPU for the Vic-20

Post by eslapion »

Schlowski wrote:Please excuse my ignorance, but changing RAm at $1000-$1FFF would mean soldering on the mainboard, right? As far as I understand the SuperCPU as implemented by Kakemons just sits in the expansion port, ready to run without modification of the mainboard - or did I miss something?
It could be done just as well with BLK 1,2,3,5 or IO2, IO3 which are accessible through the cart port.
Kakemoms wrote:Well, dual or not. The Vic-20 has now access to 24KB of expansion memory in the unit, e.g. $2000-$8000. This is shared with the 65C02. The 65C02 also have 2KB of memory from $0000-$0800 which covers the stack, zeropage and some more. Of course, this area is not viewable from the Vic-20 which has its own internal memory for that area. Thus each processor has its own stack and zeropage.

As you have already understood, there is not much for the internal MOS 6502 to do when it has a sibling running at 25MHz (I increased the speed a little today without any penalty to signal slack). But to see things on the screen you have to have it in the internal memory. Thus, to see graphics from the 65C02, the internal MOS 6502 of the Vic-20 can be used to copy bytes into the internal memory (which the 6561 VIC chip sees and can display).
It seems to me the 65C02 also doesn't have access to the 656X and 6522 registers so the MOS 6502 has to manage that for the 65C02. Hence the MOS 6502 becomes a form of memory management unit.

If I understand correctly, the MachXO3L becomes it's own computer and it's onboard 24kBytes becomes the 1st 8k to itself and the following 16K shared with the VIC-20. That's why it looks like a 16k expansion from the VIC-20's side.

What's the difference with having a W65C02 and 8k of fast SRAM covering $0000-$1FFF then 16k of dual port ram covering $2000-$5FFF vs the MachXo3L with it's 24k ?

You lose 2MHz but the result is half the price, right ? I suppose you have the added trouble of putting them on a PCB so the MachXO3L has the advantage of involving much less hardware work.

Also, if the MachXO3L is the better solution, how do the CPUs behave when both are accessing RAM between $2000-$5FFF ? Dual port RAM can manage it but how does the MachXO3L's RAM react ?
Last edited by eslapion on Wed May 17, 2017 1:27 pm, edited 2 times in total.
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