That's technical objections and they are the result of people far more qualified than me doing empirical research.Kakemoms wrote:I understand you have personal objections, but without testing we would never know what is possible.
Actually what you're doing is using an external source of current to defeat the effect of the pull down transistor of a TTL-LS chip, not NMOS.Edit: I remembered that NMOS is using a pullup resistor (load) on its output to push output high. In the event that the output is low, the NMOS transistors will pull that load as can be seen here: https://en.wikipedia.org/wiki/NMOS_logic. What we are doing here is basically pulling the same load externally. Still, testing will be the only way to make certain this is safe.
TTL-LS uses bipolar schottky transistors while NMOS uses FETs.
Since the original NMOS 6502 uses an enhancement mode FET for pull-down and a depletion mode FET for pull-up (not a resistor - TTL-LS chips do that), the way to pull down A13 with the minimum stress to components while achieving the correct logic threshold would be to pull it down no lower than 1V. That's below the threshold of 1.3~1.5V but minimizes the voltage drop. The pull-up transistor will still source the same amount of current but the power dissipated in it is Volts x current and will be lessened accordingly.