Tricking the 6502 addressing to access 54KBytes of SRAM

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Kakemoms
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Tricking the 6502 addressing to access 54KBytes of SRAM

Post by Kakemoms »

Hi

I have been looking into the schematics on the Vic-20 expansion port for some time and think I have come up with a way to trick the Vic-20 to access external SRAM for more of the addressable area. It is still untested, so I will have to test it to actually make it work, but in theory it should:

1) All expansion memory is accessed through special block signals called RAM1, 2 or 3 (1KB each) or BLK 1, 2, 3 or 5 (8KB each). You also have IO2 or IO3 (1KB each) for a total of 37KByte expansion memory.

2) The special block signals originate from three different 3-to-8 multiplexers (74LS138N) which pulls the respective line to LOW in case it is accessed. All these block signals go through a 74LS133N (1-to-13 NAND) and end up in a 74LS245 buffer that either enables or disables the databus towards the internal RAM/ROM chips. It is only possible for the 6502 to read/write data into the internal chips in the case that all RAM1,2,3/BLK1,2,3,5/IO2,3 are HIGH.

3) The 74LS138N supplies a HIGH signal on its output with a 120 Ohm internal resistor. Thus, if one pulls the output to GND at +5V, the internal resistor will limit the current to around 41mA. The max output in the datasheet is specified to 100mA for ONE output and for a maximum of 1 second. We only need 1/2 clock cycle (e.g. 500ns) so this is quite within the specification of the component.

4) By using a 1-13 NAND on all address line outputs of the expansion port it is possible to determine if the 6502 accesses a memory location that is NOT covered by the special block registers (since they all are HIGH). In such a case, the 6502 could access an external SRAM for read/write if one push a LOW signal on one of the special block lines.

Now, the missing A14, A15 on the expansion port makes it a little harder to get access to the upper 32K block, but with some logic reasoning and limitations it may be possible to access some extra KB of SRAM in this way. An interesting area would be the Character ROM (which would still be viewable from the 6560/1 side).

By reading A0-A13 we have an address that is $0000-$3FFF, e.g. a 16Kbyte area. We don't know A14 or A15. To make a logical determination we can look at all the possible memory blocks:

BLK0, 1, 2, 3, 4, 5, 6, 7

of these, BLK 1, 2, 3 and 5 gives out a signal, so without this signal, the address has to be in BLK 0, 4, 6 or 7. If A13=1 we have to be in BLK1, 3, 5 or 7 so we see that with BLK 1,2 and 5 all HIGH, the address has to be in BLK7, e.g. A14 and A15 HIGH. Thus it becomes possible to access BLK7 as SRAM which adds another 8KByte expandable. Since BLK7 is kernal this is only possible for assembly programs, so we will need a way to switch BLK7 SRAM on and off.

Edit:
This can also be used for RAM1,2,3 which resides in BLK0. If the $0400-0FFF address is accessed without any of the RAM1,2,3 signals being LOW it means that we are trying to access either BLK4 ($8400-$8FFF) or BLK6 $C400-$CFFF. The first is CHAR map and latter is Basic. Thus, we only need to choose one of them to get another 3KByte. The 6502 will not be able to differentiate, so it has to be done in assembly and one will need a way to switch it on/off as for BLK7.

The last memory location with special signal lines is IO2/3 ($9800-9FFF) in BLK4. Unfortunately, without A14 and A15 outputs, it is not possible to use these as it mirrors to $1800-$1FFF in BLK0 which is the internal SRAM memory.

An interesting aspect of getting SRAM into BLK6 ($C400-$CFFF) and BLK7 is that it would be possible to copy Kernal and Basic into the same respective SRAM locations and modify them. Thus, it would be possible to upgrade the Vic-20 kernal software-wise by using this tactic.

Total accessible memory for the 6502 in a Vic-20 with this trick would be:
BLK0-3 (32KByte)+ BLK4 (1+2KByte)+ BLK5 (8KByte)+ BLK6 (3KByte)+ BLK7 (8KByte) = 54KByte

No paging needed!
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eslapion
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by eslapion »

Looks to me like you want to make a PLA for the VIC-20.

On the C64, the 6 IO lines added to the CPU control how you use each regions of memory with a certain number of possibilities and the PLA generally does what these lines tells it to do on a cycle by cycle basis. There is also VA14 and VA15. Lines on the cartridge port can also reconfigure the memory mapping of the 64.

I suppose for many ML software it would be useful to disable the BASIC ROM and replace it with RAM. Same for the kernal.

I guess you could safely replace everything available to the CPU with RAM except for a small portion of BLK4 in which you would have access to at least one VIA which controls the memory mapping. There are 2 IO areas mapped on the cartridge port. You could reserve one of them for an extra VIA added inside the VIC for that purpose or even simpler, as I did on the Behr Bonz, a single 74LS273.
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MCes
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by MCes »

The overlap with choosing between ROM/RAM on the same address is a type of "memory paging ", so it could be better don't modify an original VIC 20 but use an external REU like this: http://sleepingelephant.com/ipw-web/bul ... 171#p83171
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Kakemoms
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by Kakemoms »

MCes wrote:The overlap with choosing between ROM/RAM on the same address is a type of "memory paging ", so it could be better don't modify an original VIC 20 but use an external REU like this: http://sleepingelephant.com/ipw-web/bul ... 171#p83171
I know that with paging you have no limit, but this is not paging. It would be directly accessible from the 6502 all the time.

To get the machine to boot, the Kernal contents would need to be in SRAM (or some other ROM image).
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by eslapion »

Kakemoms wrote:I know that with paging you have no limit, but this is not paging. It would be directly accessible from the 6502 all the time.

To get the machine to boot, the Kernal contents would need to be in SRAM (or some other ROM image).
If you use a 74LS (or HCT) 273 tied to IO3 to control the mapping, you can have this IC reset at powerup with a simple RC configuration. This way by default the VIC has a "standard" configuration.

All you'd need to make character ROM, BASIC, Kernal or other areas map to RAM is to poke a different value into IO3. All except the top half of BLK4 can be turned to RAM safely. That's a total of 60k directly accessible to the 6502 all the time... even better than 54k.
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by MCes »

Kakemoms wrote:I know that with paging you have no limit, but this is not paging. It would be directly accessible from the 6502 all the time.
6502 can see only 64k......
less 16k kernel/basic , 4k character set, 1k I/O (IO2,3 can be RAM..), 1k nibble of color RAM........
only 42K RAM could be directly addressed (internal/external RAM): imagine more memory means necessarily imagine a type of paging!
swapping ROM/RAM is paging....

Accepted that we are loking for a kind of paging the next step is make a choose on its realization....

First choise: a VIC20 unmodified (external cartridge solution),
Second choise: a VIC20 HW modify that let VIC20 at power on like unmodified.
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by eslapion »

MCes wrote:6502 can see only 64k......
less 16k kernel/basic , 4k character set, 1k I/O (IO2,3 can be RAM..), 1k nibble of color RAM........
only 42K RAM could be directly addressed (internal/external RAM): imagine more memory means necessarily imagine a type of paging!
swapping ROM/RAM is paging....
The Commodore 64 can toggle it's BASIC, Kernal, character ROM between RAM and ROM and it's no paging.

It's absolutely not true that only 42k could be adressed directly.

I have no idea what Kakemoms wants to do with this sort of trick but it can be done - easily I might add - and the total RAM you get is 60k, not 42k.

All BLK 0, 1, 2, 3, Half of 4, 5, 6, 7.

All that's required is ONE single chip like a XC9536XL as used on PLAnkton, a part of which is programmed like a 74_273 (octal D flip-flop) and a pair of 32k x 8 SRAM chips. It's a PLA for the VIC-20.
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MCes
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by MCes »

A) Concept "paging" is when at same address could correspond different memory cells, normally identified by a register.

B) 6502 can address only 64K

C) unmodified VIC20 has a memory map with 20K of ROM, 1K of I/O, 1K of color nibbles

B+C= max RAM addressable into a VIC20 is 42K RAM

A+B+C= more of 42K RAM available is paging.



NOTE:
paging is not a crime.
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by eslapion »

MCes wrote:B) 6502 can address only 64K

C) unmodified VIC20 has a memory map with 20K of ROM, 1K of I/O, 1K of color nibbles

B+C= max RAM addressable into a VIC20 is 42K RAM
WRONG... B+C= max RAM addressable into UNMODIFIED VIC20 is 42K RAM

Kakemoms wants to modify his VIC-20 and that...is not a crime.

BTW, the VIC-20 you sold me WAS modified...

It so happens that I know how to modify a VIC-20 to get the 6502 to have 60k of max adressable RAM. Am I a criminal ?

No, I just want to help the guy who started the thread achieve what he set out to do instead of telling him what he should or shouldn't do with his equipment.
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by Kakemoms »

MCes wrote:A) Concept "paging" is when at same address could correspond different memory cells, normally identified by a register.

B) 6502 can address only 64K

C) unmodified VIC20 has a memory map with 20K of ROM, 1K of I/O, 1K of color nibbles

B+C= max RAM addressable into a VIC20 is 42K RAM

A+B+C= more of 42K RAM available is paging.

NOTE:
paging is not a crime.
Well, that is the trick. I intentionally block the internal ROM access to get the 6502 to access the same area as SRAM through the expansion port. No Vic-20 modification needed.

The problem with BLK6&7 is that there are no outputs for these on the expansion port connector, so you need to deduce the logic from all the other signals.

Eslapion: how do you construct a BLK6 signal?
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by MCes »

Hi Kakemoms,
the problem of expanding RAM more than the natural areas is that old software can't use the "hidden" RAM because this RAM has not to exist for it.
Only new SW can use the new memory areas,
so: why drive crazy forcing an output and sniff the line of bus/controls on the cartridge connector searching for A14,15?
Your new SW have to manage a register for swap the RAM in ROM areas (no basic if basic-rom or kernal-rom disabled....),
are you sure that it's the best way to expand RAM?

At the same "tecnical cost" (external hardware only, SW that have to manage a "banks status register") I choose the "+123k REU" philosofy (see some post before) or similar: More RAM, no HW conflict, original ROMs always present (program that use extra RAM could be in BASIC...), ecc.....
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by Kakemoms »

MCes wrote:Hi Kakemoms,
the problem of expanding RAM more than the natural areas is that old software can't use the "hidden" RAM because this RAM has not to exist for it.
Only new SW can use the new memory areas,
so: why drive crazy forcing an output and sniff the line of bus/controls on the cartridge connector searching for A14,15?
Your new SW have to manage a register for swap the RAM in ROM areas (no basic if basic-rom or kernal-rom disabled....),
are you sure that it's the best way to expand RAM?

At the same "tecnical cost" (external hardware only, SW that have to manage a "banks status register") I choose the "+123k REU" philosofy (see some post before) or similar: More RAM, no HW conflict, original ROMs always present (program that use extra RAM could be in BASIC...), ecc.....
So your advice is basically: buy a RAM expansion?
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by Kakemoms »

eslapion wrote: WRONG... B+C= max RAM addressable into UNMODIFIED VIC20 is 42K RAM
Wrong. This is a method to get 54K RAM addressable into an UMODIFIED Vic-20. Through the expansion port.
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by MCes »

Kakemoms wrote: So your advice is basically: buy a RAM expansion?

Why buy one if you are able to plan and do it yourself?

example: put a static ram on BLK5 with MSBs address connected to userport, or use a new 6522 on cartridge drove by I/O2 or 3, or use a couple of IC to realize a R/W byte on I/O2 or 3, or......

My +123k REU link is only for indicate the approach at the problem that I think correct.
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Re: Tricking the 6502 addressing to access 54KBytes of SRAM

Post by Mike »

Kakemoms,

CA13 = 1 and also all BLK1/3/5 = 1 at the expansion port indeed are a good hint, that the 6502 accesses an address in the range $E000..$FFFF.

Now how are you going to deselect the KERNAL ROM?
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