Purpose of the vrw pin on the expansion port

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yogi
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

Richardc64 wrote:
yogi wrote: Oh, this is a bit confusing to me. I guess I had misunderstood the need for the 65245 xceivers, I thought they provided bus isolation when the 6502 was in RDY state to accommodate the VIC-1.
RDY is pulled up and unused in the VIC-20 and irrelevant to this discussion.
OK, now another question: how does the VIC-1 halt the 6502?
The rest of your summation seems correct, except that the VIA Chip Selects (internal I/O) are not qualified by Ph2, but I/O2 & I/O3 (external I/O) /CSs are. I'm not sure why the VIAs are on the BD buss, except perhaps to reduce the loading on CD.
According to Sam's CompFacts, /IO2 and /IO3 as well as the VIA chips CSs are generated by decoder UC6 which is enabled by the CA 15:13 bit pattern. So these signals would go active as soon as the address pattern matches; regardless of the clock phase. OTOH the UC5 address decoder, for the /BLK selects, is enabled every cycle by Phi2.
I am working on a Timing Diagram that won't be completely accurate, because I have to interpolate between the 6560 data sheet and several 6502 variants, but it should give a fair depiction of when things happen in the the VIC-20. In the meantime, the attached schematic may be helpful.
Thank you, your schema and notes are very helpful, much clearer then the Sam's sheets. I guess I am confused about how/when the VIC-1 accesses mem. I had assumed it did something like DMA; halting the CPU and mastering the busses, which is incorrect (?). Does it access the VA and BD busses during Phi1? (I recall that the Apple][ did video this way).
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TLovskog
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Re: Purpose of the vrw pin on the expansion port

Post by TLovskog »

The CPU is never halted. The beauty with he 6502 is that It only needs to work on one of the phases ( phi2 is high ) of the clock. Sure it starts to set up the address and r/w in the first phase but it doesn't need to. The time is enough when the clock is high and data is read or written on falling edge.

So. The other phase of the clock the VIC owns the memory bus ( separated by the buffers )


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BR
Thomas Lövskog
yogi
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

TLovskog wrote:The CPU is never halted. The beauty with he 6502 is that It only needs to work on one of the phases ( phi2 is high ) of the clock. Sure it starts to set up the address and r/w in the first phase but it doesn't need to. The time is enough when the clock is high and data is read or written on falling edge.

So. The other phase of the clock the VIC owns the memory bus ( separated by the buffers )


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Oh, This finally make sense! Thank you. I think I got off track by trying to compare the VIC to an Atari, WRONG :)
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Richardc64
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Re: Purpose of the vrw pin on the expansion port

Post by Richardc64 »

yogi wrote: According to Sam's CompFacts, /IO2 and /IO3 as well as the VIA chips CSs are generated by decoder UC6 which is enabled by the CA 15:13 bit pattern. So these signals would go active as soon as the address pattern matches; regardless of the clock phase. OTOH the UC5 address decoder, for the /BLK selects, is enabled every cycle by Phi2.
You're right. My mistake. VIAs and I/O2 and 3 are enabled when the address matches -- but curiously, I/O2-3 separate BD and CD when SØ2=1 but the VIAs enables don't! Hmmm... Being on the BD buss, I guess that would be a bad idea, huh? :roll:
yogi wrote:I think I got off track by trying to compare the VIC to an Atari, WRONG :)
Blasphemy!
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An 8 or 10-channel logic analyzer would be nice, but who has the $$$ for that?
An 8 or 10-channel logic analyzer would be nice, but who has the $$$ for that?
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"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler
yogi
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

Thanks so much, your timing diagram is great! Just what I needed.
yogi wrote:I think I got off track by trying to compare the VIC to an Atari, WRONG :)
Blasphemy!
Forgive me :lol:
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TLovskog
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Re: Purpose of the vrw pin on the expansion port

Post by TLovskog »

Very nice diagrams Richardc64! I have been thinking on doing that for very long time ... now I don't have to ...
BR
Thomas Lövskog
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