OK, now another question: how does the VIC-1 halt the 6502?Richardc64 wrote:RDY is pulled up and unused in the VIC-20 and irrelevant to this discussion.yogi wrote: Oh, this is a bit confusing to me. I guess I had misunderstood the need for the 65245 xceivers, I thought they provided bus isolation when the 6502 was in RDY state to accommodate the VIC-1.
According to Sam's CompFacts, /IO2 and /IO3 as well as the VIA chips CSs are generated by decoder UC6 which is enabled by the CA 15:13 bit pattern. So these signals would go active as soon as the address pattern matches; regardless of the clock phase. OTOH the UC5 address decoder, for the /BLK selects, is enabled every cycle by Phi2.The rest of your summation seems correct, except that the VIA Chip Selects (internal I/O) are not qualified by Ph2, but I/O2 & I/O3 (external I/O) /CSs are. I'm not sure why the VIAs are on the BD buss, except perhaps to reduce the loading on CD.
Thank you, your schema and notes are very helpful, much clearer then the Sam's sheets. I guess I am confused about how/when the VIC-1 accesses mem. I had assumed it did something like DMA; halting the CPU and mastering the busses, which is incorrect (?). Does it access the VA and BD busses during Phi1? (I recall that the Apple][ did video this way).I am working on a Timing Diagram that won't be completely accurate, because I have to interpolate between the 6560 data sheet and several 6502 variants, but it should give a fair depiction of when things happen in the the VIC-20. In the meantime, the attached schematic may be helpful.
Yogi