Purpose of the vrw pin on the expansion port

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ovale
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Purpose of the vrw pin on the expansion port

Post by ovale »

Hello,
I cannot explain by myself what is the purpose of pin 17 vr/w of the expansion port.
Could someone explain it?

Vic's address and data busses are not visible on the expansion port, so why add vrw?

Thanks,
Ovale
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Richardc64
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Re: Purpose of the vrw pin on the expansion port

Post by Richardc64 »

A better question might be why did Commodore call it "V"r/w, since the VIC IC only reads, and does not write.

VR/W is narrower than CR/W, because it is "qualified" with Phase2, and is best used for accessing expansion bus RAM.

CR/W would be used with external I/O chips that have a Phase2 pin.

(Maybe the "V" stands for Valid, not VIC?)
"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler
ovale
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Re: Purpose of the vrw pin on the expansion port

Post by ovale »

Thanks Richard,

I see your point about the use of these signals internally to the Vic20 but this still doesn't explain to me why put it on the expansion port. What is possible with this pin that otherwise would not be possible?

I found some ram expansion schematics and they use the crw pin.

http://www.mainbyte.com/vic20/e_schematic.pdf
Revision e is even more interesting because the vrw is pulled high when p1 is high (245 high impendance) and therefore it can be driven from the expansion port.
The 6560 datasheet says that during p1 the vrw must be held Hugh to avoid the Vic writes in ram.
Is this the planned use of vrw? Cause havoc :) ?
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Richardc64
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Re: Purpose of the vrw pin on the expansion port

Post by Richardc64 »

ovale wrote:I see your point about the use of these signals internally to the Vic20 but this still doesn't explain to me why put it on the expansion port. What is possible with this pin that otherwise would not be possible?
Versatility? Convenience?

If one were building some I/O device using discrete logic -- latches and such -- an already qualified WRite would be more convenient from a hardware standpoint than inverting, NANDing, NORing, etc., CR/W and Ph2.
I found some ram expansion schematics and they use the crw pin.
That works, but I've always felt VR/W was more reliable for RAM. [shrug]
http://www.mainbyte.com/vic20/e_schematic.pdf
Revision e is even more interesting because the vrw is pulled high when p1 is high (245 high impendance) and therefore it can be driven from the expansion port.
The 6560 datasheet says that during p1 the vrw must be held Hugh to avoid the Vic writes in ram.
Is this the planned use of vrw? Cause havoc :) ?
That paragraph is poorly worded. I interpret that to mean the 6560 R/W pin shouldn't be allowed to "float" during Ph1 so that any glitch doesn't cause an unintended /WRite during what should be a ReaD.

VIC-I does not initiate /WRite at any time, and I find it hard to believe that Vic's designers intended for VR/W to be externally driven low. (It would make sense if the 6502 could be tri-stated, like the C64 6510, but alas, it can't.)
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Mike
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Re: Purpose of the vrw pin on the expansion port

Post by Mike »

The main reason for VR/W on the expansion port is to provide a buffered version of the CPU R/W signal, which, incidentally is also masked in for the CPU-half of the cycle and pulled (early rev.) or driven (CR rev.) high in the other half, so errorneous writes can't occur.

The CR/W signal of the 6502 by itself is already loaded by the 245 (early rev.) or UC3 (CR rev.) and by the two R/W pins of the VIAs. RAM chips tend to have higher demands on correct timing than do have I/O chips *) - using it for RAM expansions requires an extra buffer on the cartridge. Most RAM expansions I've seen simply use VR/W instead, which also provides the same timing as for the internal RAM.

Finally, of course VIC also needs the VR/W signal to differentiate between reads and writes on its registers, when it is selected with the addresses $1000..$10FF on the VA bus.
Richardc64 wrote:It would make sense if the 6502 could be tri-stated, like the C64 6510, but alas, it can't.
You've got the cart before the horse. The extra effort necessary on the VIC-20 to build a two-tier (CPU and VIC) bus with both having access to internal RAM and character ROM is what made Commodore incorporate the bus drivers with tri-state capability into the 6510.

Still, a second busmaster demanding access to the bus has to cope with up to 3 write cycles by the 6510 which can't be interrupted, and that's why the VIC-II has to assert BA/RDY 3 cycles early before starting DMA on both halves of the cycles (for the so-called badlines and for sprite fetches).

Greetings,

Michael

*) the SRAMs are asynchronous devices, whereas the VIAs are also connected to Phi2, thus can construct an equivalent of VR/W by themselves!
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

Sorry for the bump of this thread, but I have been digging into this same topic and was about to start a new thread. So thought it better to just continue here.
After going through the Sam's CompFacts(Early Version); if I read right, VR/W= CR/W*Phi1*/Phi0 (NOTE '/Phi0' is the clock out of VIC-1, before the NOT gate that feeds to the 6502). Using Phi1 as an active LOW, but this state is longer then the active HIGH state of Phi2 (?).
/Phi0 is 180' out of phase to Phi0; so LOW when Phi0 is HIGH.
Am I right in understanding that the /WR strobe length will be based on the length of the /Phi0 LOW*Phi1 LOW? And be shorter then either of the two alone?
There must be a reason to define it in this manner rather then just VR/W= CR/W*/Phi2. Is this to insure the mem device's hold time for the ADR bus after the rising edge of /WR? I was also thinking that this design might prevented mem access during VIC-1's bus access; but does the CPU halt Phi1 during this access time?
I also noticed another related point, concerning the Adr decoding. The 'LS138, UC5, that drives the /BLK chip selects is enabled with S Phi2, so these /CS's will only be active during the HIGH period of Phi2 ; where as the 'LS138, UC6, that drives /IO 2, 3 and VIAs /CS's is enabled by ADR bits 15:13, so these /CS's will be active during the whole time the address bits match the decoder's three enables.
Would I be correct in saying that for extended adr decoding designs based on /IO2 or 3 you would need CR/W and S Phi2 for clocking latches? Or would VR/W work just as well? Or for mapping a RAM or ROM to /IO2, would the device's /CS need to be =/IO2 * /S Phi2, to avoid driving the data bus during Phi1?
Sorry for getting so far into the weeds,
Yogi
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srowe
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Re: Purpose of the vrw pin on the expansion port

Post by srowe »

yogi wrote: Would I be correct in saying that for extended adr decoding designs based on /IO2 or 3 you would need CR/W and S Phi2 for clocking latches? Or would VR/W work just as well? Or for mapping a RAM or ROM to /IO2, would the device's /CS need to be =/IO2 * /S Phi2, to avoid driving the data bus during Phi1?
Sorry for getting so far into the weeds,
Yogi
I've just been experimenting with just this and I ended up using VR/W to latch a read to an /IO port. I couldn't get a combination of CR/W and Phi2 to work.
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

srowe wrote:
yogi wrote: Would I be correct in saying that for extended adr decoding designs based on /IO2 or 3 you would need CR/W and S Phi2 for clocking latches? Or would VR/W work just as well? Or for mapping a RAM or ROM to /IO2, would the device's /CS need to be =/IO2 * /S Phi2, to avoid driving the data bus during Phi1?
Sorry for getting so far into the weeds,
Yogi
I've just been experimenting with just this and I ended up using VR/W to latch a read to an /IO port. I couldn't get a combination of CR/W and Phi2 to work.
OK Thanks. That confirms one of my questions. I'm working on a Adr decoder in /IO2 for a bank switch register and second guessing my use of VR/W.
My other concern is a RAM mapped to /IO space; as it stands now, I have the /CS tied to /IO3, /OE = /(VR/W | WP) and /WE = VR/W | WP; where 'WP' is a write protect bit. I don't know if I wrote that correct so in other words, /OE is the NOR of VR/W and WP. So except for a write cycle, /OE will be LOW most of the time. (but the RAM doesn't care the state of /OE when /WE * /CS are active, so I could just tie /OE to GND instead)
/WE is the OR of VR/W and WP, which is the negative logical AND of VR/W and WP = LOW ( the write enabled state).
Anyway my point is, this device will start driving the bus as soon as /IO3 goes low which will be some time within Phi1, until (if) /WE goes LOW. Also with the WP bit set, a write cycle will be seen by the RAM as a read cycle, so there will be bus contention for the length of that cycle as both the CPU and the RAM are driving the data bus.
I don't think that should be a problem for the CPU but not sure of the rest of the system. As I understand, Phi2 denotes when the Adr bus is stable. RD data to the CPU should hold till the end of Phi2. The /WR strobe ends before the falling edge of Phi2 so the device should complete latching the data in before the falling edge of Phi2.
I'm almost ready to test the circuit so I guess I'll have some sort of answer soon :) I may be 'over thinking' this but really don't want to fry anything.
Yogi
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Richardc64
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Re: Purpose of the vrw pin on the expansion port

Post by Richardc64 »

I am also considering banking with the option to WP selected BLKs. I see two ways to do it: By preventing the RAMs' /WE from going low, or by preventing /CS going low and thus not enabling the RAM at all. I'm leaning toward the 2nd method as it avoids buss contention -- a possibily that the VIC's designers apparently ignored, most obviously in the case of the ROMs, which get enabled regardless of the state of CR/W (or VR/W).

To avoid buss contention in my earlier expansion, all RAM /OEs were connected to an inverted CR/W preventing the RAMs from putting data on the buss while VR/W hadn't yet gone low. In the case of the ROMs, which had RAM at the same addresses, if CR/W was low the ROMs' /CS was instead directed to the RAM and the WRite would "fall thru."
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Re: Purpose of the vrw pin on the expansion port

Post by TLovskog »

Note that the databus is tristated / input on 6502 when ...

1) phi2 is low, during the R/W and Address setup.
2) During RDY states.
3) During read cycles (obviously).

The databus is driven during a write typically 150ns after phi2 goes high. Should be plenty of time for any address decoding to settle, including R/W.
BR
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

Well, I finished up the circuit and did some basic testing with it. Only a minor snafu with the '374 latch (had the CP tied to GND, and /OE tied to the gated VR/W, DUH!). With that fixed, the NVRam works fine on /IO3 so far. Only did some tests with Basic, so not the most extensive but the basic functions seem ok.

I did come up with a idea for this circuit regarding sync to Phi2, if it is needed. As I built it, /IO3 goes strait to /CS1 and I have the device's CS2 pulled to Vcc with a 10K. I did this to allow a 'expansion of the expansion', another circuit could pull CS2 low and disable this RAM so it can be inserted into /IO3 space. But if I routed S Phi2 to CS2 this would sync the RAM to the system without having to add another gate on this board.
Richardc64 wrote:I am also considering banking with the option to WP selected BLKs. I see two ways to do it: By preventing the RAMs' /WE from going low, or by preventing /CS going low and thus not enabling the RAM at all. I'm leaning toward the 2nd method as it avoids buss contention -- a possibily that the VIC's designers apparently ignored, most obviously in the case of the ROMs, which get enabled regardless of the state of CR/W (or VR/W).
The first option seems to work with what I've tested so far, but my tests were simple so not anywhere near the speed of ML back to back accesses.
Your second option is interesting and I hadn't considered that approach.
Yogi
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

TLovskog wrote:Note that the databus is tristated / input on 6502 when ...

1) phi2 is low, during the R/W and Address setup.
2) During RDY states.
3) During read cycles (obviously).

The databus is driven during a write typically 150ns after phi2 goes high. Should be plenty of time for any address decoding to settle, including R/W.
Oh, this is a bit confusing to me. I guess I had misunderstood the need for the 65245 xceivers, I thought they provided bus isolation when the 6502 was in RDY state to accommodate the VIC-1. As Mike pointed out above, the 6510 included tri state busses for this reason.
Most all designs I've seen for 6502 based systems, qualify R/W with Phi2 in some way to avoid spurious mem writes during the Adr and Data bus setup in Phi1. Of course the VIC-20 is unique with the VIC1, and I've yet to fully understand the timing of this machine :)
To sum up;
VR/W valid during Phi2, always High unless /WE active
CR/W not qualified by Phi2, state unknown during Phi1
/BLKx only active during Phi2
/RAMx only active during Phi2 (via VA xceivers)
/IOx not qualified by Phi2, active whenever CAdr 15:10 bit pattern matches
CA and CD busses not qualified with Phi2
VA and BD busses are qualified with Phi2
Are these defs correct?
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Re: Purpose of the vrw pin on the expansion port

Post by TLovskog »

It is two different things. The data buss has to tristste on all 65xx internally regardless. VIC 20 also have buffers for isolating VIC chip and 6502. Both data AND address. The 6510 has an additional tristate capability for the address bus also, thus eliminating these external buffers.
BR
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Re: Purpose of the vrw pin on the expansion port

Post by Richardc64 »

yogi wrote: Oh, this is a bit confusing to me. I guess I had misunderstood the need for the 65245 xceivers, I thought they provided bus isolation when the 6502 was in RDY state to accommodate the VIC-1.
RDY is pulled up and unused in the VIC-20 and irrelevant to this discussion. The rest of your summation seems correct, except that the VIA Chip Selects (internal I/O) are not qualified by Ph2, but I/O2 & I/O3 (external I/O) /CSs are. I'm not sure why the VIAs are on the BD buss, except perhaps to reduce the loading on CD.

I am working on a Timing Diagram that won't be completely accurate, because I have to interpolate between the 6560 data sheet and several 6502 variants, but it should give a fair depiction of when things happen in the the VIC-20. In the meantime, the attached schematic may be helpful.
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Re: Purpose of the vrw pin on the expansion port

Post by yogi »

TLovskog wrote:It is two different things. The data buss has to tristste on all 65xx internally regardless. VIC 20 also have buffers for isolating VIC chip and 6502. Both data AND address. The 6510 has an additional tristate capability for the address bus also, thus eliminating these external buffers.
Thanks TLovskog, I stand corrected, still working out the differences.
Yogi
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