Thinking of a SuperCPU VIC

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eslapion
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Thinking of a SuperCPU VIC

Post by eslapion »

I just took a careful look at the schematic of the VIC and the 6502 doesn't have a BE line.

Also, the cart port is missing a couple of address lines.

Therefore, the only way I see to make a functional SuperCPU for the VIC is by replacing the 6502... the accelerator would have to plug in the CPU socket.

Assuming we sometimes want to disable the acceleration, the W65C02S appears to be able to run at the slower 1MHz speed.

Even if we were to reroute A14 and A15 to the two NC lines of the cart port, I don't know of a way to make a standard NMOS 6502 go tristate on its adress/data/RW lines when the external faster CPU would want to access the bus.
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Post by Mike »

That's what I wrote in another thread last year:
vk4akp wrote:- Super CPU. (Something no one seems to have thought of yet for the Vic!)
Mike wrote:You might take a look at the thread 'The VIC-20 at 10 Mhz'. If it were implemented for the VIC-20, it would be an internal mod, for a good reason: an external cartridge cannot access the built-in RAM - for the same reason the VIC chip cannot access external memory: there are three 74LS245 buffers acting as timing barrier in-between. And you'd surely want the 'Super CPU' to access the video memory, right?
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Post by eslapion »

Mike wrote: an external cartridge cannot access the built-in RAM - for the same reason the VIC chip cannot access external memory: there are three 74LS245 buffers acting as timing barrier in-between. And you'd surely want the 'Super CPU' to access the video memory, right?
There is something wrong with what you're saying here.

The only reason why the built-in RAM cannot access the internal memory is because of the missing address lines. With these added to pins 20 and Y of the cart port then all 64k range is externally accessible.

If the 6502 is removed from its socket and the missing address lines are added to the cart port then all the connections to the CPU socket are available on the cart port except two clock lines.

The REAL reason why you can't have an accelerator on the cart port is not because you cannot access the built-in RAM (in fact, you can, given the extra address lines). Its because the native 6502 of the VIC, the NMOS version doesn't support DMA. It won't leave its bus available to another CPU or accessing device.

As for the 6560/6561 not having access to external memory, that's the way it is right now when you have 3k/8k/16k/24k/32k ram expansions so not much of a deal.

The 74LS245 have no importance whatsoever. They prevent the 6502 accessing the RAM when the VIC is reading from it but when the clock is in the proper phase, the 6502 can access everything and so could anything on the cart port given you could turn all address/data/RW lines on the 6502 to high impedance, which you cannot with the NMOS version.
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Post by Mike »

eslapion wrote:The only reason why the built-in RAM cannot access the internal memory is because of the missing address lines.
Huh? What are you trying to say with that? RAM does not actively access anything.
With these added to pins 20 and Y of the cart port then all 64k range is externally accessible.
You surely can provide A14 and A15 to extern devices. That does not alter the fact, that the 6502 is busmaster. It alone drives A0 .. A15.

Furthermore CR/W and VR/W are driven by internal logic, like the BLK and RAM signals. They're outputs, an external cartridge is not supposed to drive these signals!
The 74LS245 have no importance whatsoever. They prevent the 6502 accessing the RAM when the VIC is reading from it but when the clock is in the proper phase, the 6502 can access everything and so could anything on the cart port given you could turn all address/data/RW lines on the 6502 to high impedance, which you cannot with the NMOS version.
To clarify things:

- Two 74LS245 separate the address bus, whenever the VIC is going to access RAM or the character ROM. Whatever is then present on the cartridge port is still the current address put there by the 6502.

- The 74LS245 on the data either separates the two data busses, again, when VIC accesses the internal RAM or the character ROM. It also separates the bus, when the 6502 accesses external memory (see UD9) or BLK 6/7 (BASIC/KERNAL ROM), as the address lines for the memory on the VIC's side of the data bus are not fully decoded (only 14 bits wide, with "A13" on the VIC address bus being the negate of A15 on the CPU address bus) and so would interfere with data put on the data bus by external devices or the ROMs. When the 6502 accesses internal RAM or the character ROM, the buffer direction is selected as appropriate.
If the 6502 is removed from its socket and the missing address lines are added to the cart port then all the connections to the CPU socket are available on the cart port except two clock lines.
Then you end up with what I wrote anyway, and you can quite as well stick the Super CPU into the empty socket. Then however, you also don't have to supply A14 and A15 to the cartridge port.

BTW, on a CR VIC-20 the pin Y carries audio in.

Even if you supply the address lines A14 and A15 to the cartridge port, so an external CPU could drive the whole address bus, that does not obviate the need to remove the 6502. However, the Phi1 and Phi2 signals would also be missing when the 6502 is removed, as those are supplied by the 6502, as you wrote.
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Post by eslapion »

Mike wrote:
eslapion wrote:The only reason why the built-in RAM cannot access the internal memory is because of the missing address lines.
Huh? What are you trying to say with that? RAM does not actively access anything.
Oops, bad wording.

Lets repeat that.

The only reason why the built-in RAM cannot BE ACCESSED from the cart port is because of the missing address lines...
You surely can provide A14 and A15 to extern devices. That does not alter the fact, that the 6502 is busmaster. It alone drives A0 .. A15.
Isn't that what I was saying later on?
Furthermore CR/W and VR/W are driven by internal logic, like the BLK and RAM signals. They're outputs, an external cartridge is not supposed to drive these signals!
VR/W is driven by internal logic, CR/W is NOT... It is driven by the 6502 and if the 6502 is removed then it can be driven externally.
To clarify things:
You are repeating things I already knew...
If the 6502 is removed from its socket and the missing address lines are added to the cart port then all the connections to the CPU socket are available on the cart port except two clock lines.
Then you end up with what I wrote anyway, and you can quite as well stick the Super CPU into the empty socket. Then however, you also don't have to supply A14 and A15 to the cartridge port.
My point is, if you can make a SuperCPU on the cart port instead of the CPU socket then you can make one that will actually fit on all VICs and not cause space conflicts on many of them.
BTW, on a CR VIC-20 the pin Y carries audio in.
That I didn't know. It is certainly not documented in the Programmer's reference guide which has the schematics of the 2 prong version.
Even if you supply the address lines A14 and A15 to the cartridge port, so an external CPU could drive the whole address bus, that does not obviate the need to remove the 6502. However, the Phi1 and Phi2 signals would also be missing when the 6502 is removed, as those are supplied by the 6502, as you wrote.
Could it be possible to replace the 6502 with a simple logic chip mounted on a 40 pin socket?

This would deal with these clock signals.

BTW, I'm still not saying to you what I REALLY have in mind for a SuperCPU VIC which is considerably simpler than the 65816 accelerator mentioned in your other thread.
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Post by TLovskog »

My take on that would be that since you would have to add the missing A14/A15 to the port (and having in some cases only one spare pin) you still need to make modifications to the VIC-20. Then you could just as well create a replacement for the CPU itself.

There are plenty of room around the CPU socket for a tiny board with SMT parts, to make that work for all (2?) versions of the mainboard.
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Post by Mike »

eslapion wrote:You are repeating things I already knew...
Yes. I wrote these two paragraphs to assure you that I know, too.

What I tried to say, can maybe brought down to these two statements:

1. As long as the 6502 is still on the motherboard, it is busmaster on the cartridge port.

2. If you remove the 6502, you can quite as well use its socket for a small board carrying the replacement CPU - why complicate it further by extra connections to the cartridge port, maybe a logic board in the CPU socket and then an external CPU cartridge?
I'm still not saying to you what I REALLY have in mind for a SuperCPU VIC which is considerably simpler than the 65816 accelerator mentioned in your other thread.
Whatever you have in mind, it also has to deal with the minimum allowed 300 ns or 400 ns cycle time of the internal RAM.

I have an idea, which would require no internal mods: attach some higher clocked 65xx CPU to the expansion port, allow both CPUs to access the external RAM through some bus arbitration unit. The 6502 in the VIC-20 could see the external RAM as 8 times 8K blocks, mapped into, say, BLK3 over a banking register, and control the external CPU as being stopped, free-running (max-speed), 1 MHz synchronous, single-step, reset. Finally, you use the VIC-20 console as terminal, modifying the external RAM as necessary to feed the external CPU with data, and reading out the external RAM likewise, to display parts of it on the screen of the VIC-20 (text or bitmapped).

It is clear that this solution will not accelerate existing software, rather new software would need to be written for it.

A similar approach was once taken by Acorn with their second processor modules.
Last edited by Mike on Sat Oct 29, 2011 9:24 am, edited 1 time in total.
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Post by eslapion »

Mike wrote:2. If you remove the 6502, you can quite as well use its socket for a small board carrying the replacement CPU - why complicate it further by extra connections to the cartridge port, maybe a logic board in the CPU socket and then an external CPU cartridge?
Quite simply because it doesn't fit...

Even a simple JiffyDOS won't fit in the older 2 prong VIC and that got me biting my fingernails to the blood once I realized I sold a couple of these.
I'm still not saying to you what I REALLY have in mind for a SuperCPU VIC which is considerably simpler than the 65816 accelerator mentioned in your other thread.
Whatever you have in mind, it also has to deal with the minimum allowed 300 ns or 400 ns cycle time of the internal RAM.
Well, assuming you have all the same SO2,address, data and RW lines on the cart port as on the 6502 socket, so would anything on the 6502 socket.
I have an idea, which would require no internal mods: attach some higher clocked 65xx CPU to the expansion port, allow both CPUs to access the external RAM through some bus arbitration unit. The 6502 in the VIC-20 could see the external RAM as 8 times 8K blocks, mapped into, say, BLK3 over a banking register, and control the external CPU as being stopped, free-running (max-speed), 1 MHz synchronous, single-step, reset. Finally, you use the VIC-20 console as terminal, modifying the external RAM as necessary to feed the external CPU with data, and reading out the external RAM likewise, to display parts of it on the screen of the VIC-20 (text or bitmapped).

It is clear that this solution will not accelerate existing software, rather new software would need to be written for it.

A similar approach was once taken by Acorn with their second processor modules.
How about a cart with only 2 extra connections (A14 and A15) with a W65C02S on it. This CPU runs at 10 or 14 MHz.

On it is a copy of all ROM data contained in the VIC and perhaps a modified version of the Kernal ROM. However, the ROM chip on the accelerator is rated for 45ns. This accelerator also contains its own RAM, 32k of it or more, covering BLK0-1-2-3. Maybe BLK5 too.

Whenever this CPU acceses its RAM or a copy of the ROM data, it runs at full speed. Only when it tries to access the upper half of BLK0 (video RAM) or the upper half of BLK4 (VIAs and the VIC's registers) does it have to slow down to a 1MHz access cycle.

The 6502 in the VIC would be removed and replaced with a simple little board with a logic chip on it to deal with the clock signals the same way a real 6502 would but it would also add the 2 necessary taps to send the A14-A15 to the external accelerator.

Of course, since the external CPU has access to all the same lines as the original 6502, disabling acceleration only implies flipping a switch to clock it down to the original speed and making all accesses go back to the original hardware and kernal. All accesses are 1MHz now and the faster CPU accesses the original ROMs instead of its own modded ones.

I tought of using the VIC-20 as a terminal to another CPU but its slow and actually requires more hardware. Also, from a software point of view, it is a LOT more complicated.
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Post by eslapion »

TLovskog wrote:There are plenty of room around the CPU socket for a tiny board with SMT parts, to make that work for all (2?) versions of the mainboard.
This is true of the VIC-20 Cr. Not so with the original 2 prong version.

Space is at an incredible premium around the 6502 and BASIC/KERNAL ROMs in the older models because of the huge heat sink of the internal power supply.
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Post by TLovskog »

Double post
Last edited by TLovskog on Sat Oct 29, 2011 8:16 am, edited 1 time in total.
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Post by TLovskog »

Double post ... well actually for some reason it appeared in tripplets. Sorry.
Last edited by TLovskog on Sat Oct 29, 2011 8:17 am, edited 1 time in total.
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Post by TLovskog »

TLovskog wrote:This is true of the VIC-20 Cr. Not so with the original 2 prong version.

Space is at an incredible premium around the 6502 and BASIC/KERNAL ROMs in the older models because of the huge heat sink of the internal power supply.
Well I suppose we have different experiences. I was refering to the old 2-Prong version also.

I would say that there are oceans of room. There would easilly fit a board extending / wideing sligthly to left of the cpu and over UD8, UE8 and UF8. Around 4000mm2 with only one sided mounting. An additional 3000 mm2 if we use double sided mounting. The CPU, FPGA (supporting glue logic) and all RAM/FLASH you can think of would only consume 1000-1500mm2 without using any exotic packages.

So I would say there are plenty of room.
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Post by eslapion »

With a standard JiffyDOS for VIC on the Kernal ROM, I can't close the case anymore.

You open the case and it LOOKS like you've got lots of space there but the vertical clearance is minuscule.

I had to custom design my own JiffyDOS with ultra low profile sockets and pin headers otherwise I couldn't close the case anymore as the PET style keyboard is internally thicker than the standard C64 style keyboard.

My old style VIC is like this:
http://www.old-computers.com/museum/pho ... c=252&st=1
(Click on "Inside VIC-20" and pay close attention to items 6 and 7)

The keyboard, on top of being thicker, is slanted so there is less clearance on the forward edge and that is exactly where the 6502 is located. I have an early PAL VIC-20 here and the chips location is the same.

If you put anything of standard dimensions in the CPU socket on either of these machines, you must change the keyboard or leave the case open at all times.
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Post by eslapion »

Haa man... I can't believe this.

I started this thread because I was all too eager and happy to have found solutions to the problem of not being able to fit an accelerator inside the VIC and because I had already considered using the VIC as a terminal to a faster imbedded computer but found a better solution and what do I get?

Instead of getting help moving forward with this idea I'm being told that...
- I should use the VIC as a terminal for an imbedded computer
- There is enough space to fit an accelerator inside the VIC

Duh!!
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Post by Mike »

Save quoting the original post of this thread and your last post in full:

- In the OP, you state:
eslapion wrote:Therefore, the only way I see to make a functional SuperCPU for the VIC is by replacing the 6502... the accelerator would have to plug in the CPU socket.
which just was confirmed by me in the post below that, pointing you to another solution, followed by a small argument about the bus buffers.

It was only a lot time later in this thread, after my last post, that you explicitly stated your concern about fitting the extension into 2-prong VICs:
eslapion wrote:Quite simply because it doesn't fit...
Nice.

Assuming your project is still in the beer-and-pizza phase, I thought you were open for suggestions and maybe hints how to proceed further. If you are not able to handle such a discussion, and reply alongside the second paragraph in your last post above:
eslapion wrote:Instead of getting help moving forward with this idea I'm being told that...
- I should use the VIC as a terminal for an imbedded computer
- There is enough space to fit an accelerator inside the VIC

Duh!!
... then I gladly confess that unless you present a hardware prototype I am not going to contribute to the discussion in this thread any further.
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