6562/6563 datasheet

[eslapion]

... and neither is it about dreaming of non-existent hardware.

I persist... there is hardware available right now that could replace just about any 65XX/85XX series of chips ever made by Commodore.

What do you think is inside the chameleon 64? I am absolutely convinced those types of chips or even the Spartan family used in the 1541 U/U2 could be used to make a new video chip for the VIC-20 that supports 40x25 display.

Its only a matter of missing technical information to program them. You can't tell me these chips don't exist, anyone who can browse through Digikey's online catalog can find them in a few minutes.

... unless you've been in Denial for the last few decades...

hummm...

Yeah, well, I guess that's what we all come here for... isn't it?

[Kakemoms]

Well, going back to the not so pointless discussion of the datasheet, I see that the pin 37 of the 6562/6563 had 3 different options for connection. On the 6560/6561 it was the 2MHz memory clock (also an option). The Bus Available option of the 6562/6563 would have made it possible to give the processor access to the SRAM between screen lines (and possibly after the last screen line) without having to upgrade the SRAM chips. But it would have given a 40 column Vic-20 with a very slow CPU memory access.

The only other way to upgrade an existing Vic-20 with this chip would be to replace the SRAM chips, ROM chips and 6502?

Edit: Thinking more about it, would the 6562/6563 have been backwards compatible without the 2MHz memory clock?

[eslapion]

The Bus Available option of the 6562/6563 would have made it possible to give the processor access to the SRAM between screen lines (and possibly after the last screen line) without having to upgrade the SRAM chips. But it would have given a 40 column Vic-20 with a very slow CPU memory access.

Now that certainly seems similar to the VIC-II's way of doing things...

[Kakemoms]

The Bus Available option of the 6562/6563 would have made it possible to give the processor access to the SRAM between screen lines (and possibly after the last screen line) without having to upgrade the SRAM chips. But it would have given a 40 column Vic-20 with a very slow CPU memory access.

Now that certainly seems similar to the VIC-II's way of doing things...

You are thinking about the Max machine?

[eslapion]

You are thinking about the Max machine?

Nope.

On the C64, instead of having a double speed bus as seems to be required by the 6562/63, the VIC-II "steals" 40 cycles from the CPU for every line of text. That's a total of 40*25=1000 cycles every video jiffy; 60'000 stolen cycles per second on NTSC, 50'000 stolen cycles per second on PAL. This represents a small 5-6 % slower; not too bad.

If you use the 6562/63 at the same bus speed found in a VIC-20/C64, this chip unlike the 6567/69 doesn't have a 40 bytes cache so it would steal 40 cycles from the CPU on every scan lines there is text or graphics to display if you use BA to manage bus access between CPU and video chip. That's a total of 40*200=8000 cycles every video jiffy.

In the NTSC world, that's 480'000 stolen cycles per second. In PAL, that's 400'000 stolen cycles per second. This would indeed result in a very slow machine.

[Kakemoms]

You are thinking about the Max machine?

Nope.

On the C64, instead of having a double speed bus as seems to be required by the 6562/63, the VIC-II "steals" 40 cycles from the CPU for every line of text. That's a total of 40*25=1000 cycles every video jiffy; 60'000 stolen cycles per second on NTSC, 50'000 stolen cycles per second on PAL. This represents a small 5-6 % slower; not too bad.

If you use the 6562/63 at the same bus speed found in a VIC-20/C64, this chip unlike the 6567/69 doesn't have a 40 bytes cache so it would steal 40 cycles from the CPU on every scan lines there is text or graphics to display if you use BA to manage bus access between CPU and video chip. That's a total of 40*200=8000 cycles every video jiffy.

In the NTSC world, that's 480'000 stolen cycles per second. In PAL, that's 400'000 stolen cycles per second. This would indeed result in a very slow machine.

Oh, I see. So the Max and C64 are essencially the same with regard to 6510/video bus multiplexing? I thought I read here that the Max didn't do memory multiplexing with the 6566 video chip... but that would make it hard to display C64 gfx without a higher clock speed or very slow cpu..

[eslapion]

Oh, I see. So the Max and C64 are essencially the same with regard to 6510/video bus multiplexing?

I know nothing of the Max machine and nothing I said was about the Max machine.

[Kakemoms]

Every C64 can run Max cartridges in "Max" mode, so it would incur that they work the same way when this mode is enabled. As the first Max had 6566 video it is anyway interesting as for the evolution of the Vic-I chip?

[eslapion]

Every C64 can run Max cartridges in "Max" mode, so it would incur that they work the same way when this mode is enabled. As the first Max had 6566 video it is anyway interesting as for the evolution of the Vic-I chip?

The Programmer's Reference Guide of the C64 has information about the 6566 and the only major difference I can see it that it was designed for static RAM and therefore doesn't use a multiplexed address bus.

That being said, it changes absolutely nothing to the speed of the CPU/video shared bus.

Also, the "Max" mode which is supported by the C64 is just a different memory mapping for the CPU. It has no impact at all on the video chip.

Oh, I see. So the Max and C64 are essencially the same with regard to 6510/video bus multiplexing?

AFAIK, you are confusing 2 completely different things here.

The bus is shared between CPU and video chip. The 6567 does address multiplexing for compatibility with DRAM but it changes nothing to the sharing and bus speed.

[Kakemoms]

The Vic-20 uses SRAM and has a time-division-multiplexing between the 6502 and 6561. So yes, it has multiplexing.

DRAM multiplexing is only to reduce the number of address lines by alernating the LSB and MSB. You still need to do time-division multiplexing to allow two IC's to access it, but differently.

But from the way I read your posts you are thinking of the first way as "sharing" and the DRAM LSB/MSB multiplexing as "multiplexing"?

Sorry for the confusion but I am a physicist.

[eslapion]

The Vic-20 uses SRAM and has a time-division-multiplexing between the 6502 and 6561. So yes, it has multiplexing.

Say what???

The 6502 uses one half of every clock cycle while the 6560/61 uses the other half. This is not multiplexing, unless you desperately want to confuse everyone.

[Kakemoms]

The Vic-20 uses SRAM and has a time-division-multiplexing between the 6502 and 6561. So yes, it has multiplexing.

Say what???

The 6502 uses one half of every clock cycle while the 6560/61 uses the other half. This is not multiplexing, unless you desperately want to confuse everyone.

No I don't confuse "everyone" since as per definition, anything that shares the same line is multiplexing. See https://en.wikipedia.org/wiki/Time-divi ... ltiplexing or http://whatis.techtarget.com/definition ... lexing-TDM.

So yes, using the same line at different clock phases of a 1MHz clock to access the SRAM at 2MHz is certainly multiplexing.

[eslapion]

No I don't confuse "everyone" since as per definition, anything that shares the same line is multiplexing. See https://en.wikipedia.org/wiki/Time-divi ... ltiplexing or http://whatis.techtarget.com/definition ... lexing-TDM.

So yes, using the same line at different clock phases of a 1MHz clock to access the SRAM at 2MHz is certainly multiplexing.

I have the good old VIC-20 Programmer's reference guide here.

It is mentioned in there the databus and address bus are shared between the CPU and video chip. The word "multiplexing" is not even mentioned in the index.

So when you first mentioned that, I thought you were saying there is a difference in bus speed between the C64 and the VIC-20 because the C64 multiplexes the address bus for DRAM compatibility.

So yes, if you want to confuse people, by all means create your own expressions, disregard past naming conventions and create your own nomenclature.

Please see page 110 of the VIC-20 P.R.G. figure 3-1

[Kakemoms]

Multiplexing is a terminology that has nothing to do with RAM and was used even before anyone made DRAM. In fact, the first DRAM didn´t even use multiplexing.

If you had read the links I sent, you would have known that:
"Time-division multiplexing is used primarily for digital signals, but may be applied in analog multiplexing in which two or more signals or bit streams are transferred appearing simultaneously as sub-channels in one communication channel, but are physically taking turns on the channel."

The VIC chip even applies time division multiplexing internally to make the video signal, so I don't understand why you are so onset on using the term on DRAM only. In fact I advice you to read about multiplexing so that you might understand what its all about instead of dismissing it as a DRAM terminology, which it is not.

[groepaz]

The 6502 uses one half of every clock cycle while the 6560/61 uses the other half. This is not multiplexing, unless you desperately want to confuse everyone.