6560 FPGA Progress.

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JonBrawn
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6560 FPGA Progress.

Post by JonBrawn »

This week I finally managed to get video output from the FPGA when it is connected up in place of the 6560 in my VIC-20.
IMG_4864.jpeg
(The loose grey & white wires are deliberate).
Working on FPGA replacement for 6560/6561
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Re: 6560 FPGA Progress.

Post by joshuadenmark »

Wow 😮 looks very promising. Will be following your project.
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Re: 6560 FPGA Progress.

Post by beamrider »

impressive
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Re: 6560 FPGA Progress.

Post by JonBrawn »

...and now the sheer number of individual wires flying from VIC-20 to board to board to board now means that I'm spending more time looking for which wire has become detached than making actual progress, so I'm going to spin a first PCB so I can continue adding features instead of guessing which wire is broken.
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Re: 6560 FPGA Progress.

Post by joshuadenmark »

Great idea, get rid of the birds nest.
Kind regards, Peter.
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Re: 6560 FPGA Progress.

Post by JonBrawn »

The PCB for interfacing my FPGA development board to the 40-pin DIP socket for the 6560 is now being manufactured. It's a bit of a monster at 120mm x 66mm when you compare it to a 6560, but it will allow me to finish writing the Verilog RTL for the FPGA.

Meanwhile, I'm still looking for a suitable FPGA to use in the actual design, but it's proving hard to find one that:

- is available
- has 70+ I/Os
- has 2500+ LUTs
- has 5V tolerant I/Os
- has open-drain I/Os available
- has free development tools
- over 700 registers (so nothing in the XL9500XL series)

In other news, I am now the proud owner of a PAL Vicky 20, so I can do the same in-depth analysis of the 6561 PAL video format as I did for the 6560 NTSC video. Given that my PAL to HDMI converter box totally loses its lunch on the VIC's PAL signal I'm going to assume that it has some of the same quirks as the 6560 NTSC.
Working on FPGA replacement for 6560/6561
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Re: 6560 FPGA Progress.

Post by nbla000 »

I don't know if this old thread may help you.
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Re: 6560 FPGA Progress.

Post by Vic20-Ian »

The Vic20 is running in MiSTer FPGA on DE10 Nano.

There may be somethings you can glean from there.

https://misterfpga.org/
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Re: 6560 FPGA Progress.

Post by JonBrawn »

nbla000 » I don't know if this old thread may help you.
Oh yes, that has been a great help, as have various comments from "mike" (though he might not know it).
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Re: 6560 FPGA Progress.

Post by JonBrawn »

Vic20-Ian » The Vic20 is running in MiSTer FPGA on DE10 Nano.
I'm designing a drop-in replacement for the 6560 / 6561 VIC chip, which has different constraints to those on the MiSTer FPGA. The main issue I'm having when looking for devices is that most of the ones that are currently available are also currently stonkingly expensive, and those that you could get from AliExpress et al. are no longer supported by the various toolchains, and the older toolchains that do support them won't run on any of the OSs I can get my hands on (who would have guessed RedHat 6 would be so hard to obtain?!). Argh!

I've got all of the video generation sorted out for the NTSC version, including the right kinds of DACs. I have to finish implementing functionality such as multi-color mode and double-height characters, but progress has come to a screeching halt while I get a PCB re-made up to replace the unreliable mess of wires and breadboard I've been using to date [the first PCB had some, erm, mistakes that made it completely unusable]. That board is now designed and ordered (the shipping is three times the cost of the PCBs!), so while I'm waiting for that to come in the post, I'm going to start working out the differences and similarities between NTSC and PAL composite video. I'm looking forward to finding out why NTSC needs a 14.<mumble> MHz clock, but PAL only needs a 4.<mumble> MHz clock, and how the heck that 4.<mumble> MHz gets turned into a useful dot clock.
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Re: 6560 FPGA Progress.

Post by Mike »

Vic20-Ian wrote:The Vic20 is running in MiSTer FPGA on DE10 Nano.
A complete emulation of a computer, be it a software-only as in VICE or as combination of hardware and software in a FPGA has substantially relaxed timing requirements, as ultimately 'just' each screen frame has to be completed within a 1/60 or 1/50 second, and sound can be buffered, so both keep in sync.

A drop-in replacement for a video chip has much stricter timing requirements. Whatever comes from the surrounding computer, and whatever goes to the computer, has to be handled on the sub-microsecond time scale, and the type of logic to handle this is at least somewhat different than what you can get away with, say, the MiSTer VIC-20 core.
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Re: 6560 FPGA Progress.

Post by beamrider »

There are different integrities of FPGA "emulation".

Some are of the type you mention, "black-box" and only have to render correct audio/video. Other's let's call them "glass-box" have been modelled on actual circuits reproducing the exact same gates which I expect will have almost identical timing to the original, but obviously you can't model the length of traces etc.

I am lead to believe, some of the Jotego cores on Mister fall into the "glass-box" category.
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Re: 6560 FPGA Progress.

Post by JonBrawn »

I now have an interface PCB replacing the multi-story interface breadboard mess I was using - SMT devices, hand soldered (something I've never done before, which is why I did it - next time it's being popped in the toaster-oven-on-steroids).

Those 14MHz clocks really hate the 100mm ribbon cable though - if you look at the pinout of the 6560/61 and imagine that mapped onto a 40-pin IDC cable, near the pin 1 end you get ..., CHROMA, XTAL_P1, LUMA, XTAL_P2, ... so not the best neighbors.

I'm toying with the idea of not bothering with the Interlace bit's functionality in register $9000 - is it of any practical use whatsoever? Do any of the demos use it to do interesting things?
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Re: 6560 FPGA Progress.

Post by Mike »

JonBrawn wrote:I'm toying with the idea of not bothering with the Interlace bit's functionality in register $9000 - is it of any practical use whatsoever? Do any of the demos use it to do interesting things?
Please check out the thread NTSC interlace detail info needed, and parts 12, 13 and 16 of the New Frontiers in VIC-Hires-Graphics Series, where interlace is used to double the vertical resolution with the NTSC VIC-I. Without this, your FPGA re-implementation would be incomplete.
Those 14MHz clocks really hate the 100mm ribbon cable though - if you look at the pinout of the 6560/61 and imagine that mapped onto a 40-pin IDC cable, near the pin 1 end you get ..., CHROMA, XTAL_P1, LUMA, XTAL_P2, ... so not the best neighbors.
Interleaving GND wires in-between those signals on the ribbon cable works wonders. ;)
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Re: 6560 FPGA Progress.

Post by JonBrawn »

Interleaving GND wires in-between those signals on the ribbon cable works wonders
I know! I'm wondering about those fancy-dancy 80 conductor IDE cables - I haven't researched which pin(s) it thinks are ground connections yet, and if it's using anything other than the actual ground pin from the VIC 6560 then it'll be worse than not having them.

I've now got a 30mm cable, and I'm finally getting some clock pulses through, but the combination of the cable and the level shifters I'm using is messing up those pulses. Currently, I'm timing everything using the FPGA development board's on-board 100MHz oscillator (which does NTSC remarkably well), but I really need to be getting the clock from the motherboard so that the RF trimmer works for shifting the frequency around.
Working on FPGA replacement for 6560/6561
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