Today I'm posting some details about the base address computation section of the 6561, i.e. the bit that calculates the output values for address lines A9 to A13. It is highlighted with a pink box in the following die shot image:
As you can see, it is a rather large area below the video matrix counter and latch, and to the left of the cell index logic. The following image shows a close up of that section of the die shot with the diffusion, polysilicon, and contacts identified:
Unfortunately it is so large that it is difficult to see most of the labels. The eight lines coming in from the bottom edge of the image towards the bottom right corner are the eight bits of the base address control register, i.e. CR5. They are not in numerical order though. To better support the layout of this section of the die shot, the 8 bits of that control register are stored in order from left to right: BC12, BV11, BC11, BV10, BC10, BC13, BV12, BV13 (i.e. in bit order 2, 5, 1, 4, 0, 3, 6, 7). The other base address value, BV9 from bit 7 of CR2, is coming in on a metal line partway up on the right edge.
Further up on the right hand edge, we have BM9, BM10, and BM11 that are from the cell index logic that we looked at a few posts ago. These three values are used in the computation of the values for address lines A9 to A13.
From the top edge and towards the top left corner, we having coming down on two metal lines VMC10 and VMC11. These are bits 10 and 11 of the video matrix counter. These values are also used in the calculation of the values for address lines A9 to A13.
In the bottom left corner are the outputs from this base address computation section, i.e. the inverse of the values intended for address pins A9 to A13. Although I haven't checked this yet, I think they're the inverse values because the output sections of the relevant bonding pads will probably inverse the values again prior to leaving the chip.
The rest of this section of the die shot is made up of adders and pass transistor logic. The HCC0 signal and its inverse HCC0' are used to control the pass transistors. We can see HCC0 coming in at the bottom right corner, where it is inversed, then both HCC0 and HCC0' weave left almost the whole way across the image, and then head upwards, and they connect to many pass transistors along their path.
Having said all the above, let's take a look at the logisim diagram:
As is normally the case, you will certainly need to click on the image to get a better look. At the top we have five adders. I have numbered them from 1 to 5, with the main logic gates used in each adder being labelled with the relevant number. I have labelled them in their sequence order, i.e. the carry output from adder 1 is an input to adder 2, the carry from adder 2 an input to adder 3, and so on. I have placed the adders in the logisim diagram in the same order as they appear on the die shot. As you can see from this, they are not laid out in numerical order. Adder 1 is in the middle, adder 2 on the far left, etc. This is probably because of where the corresponding inputs are coming from.
Let's take a closer look at the adders. Four of the five adders are actually half adders. Only adder 2 is a Full Adder. If you look at the inputs to the other four adders, you'll notice that they only have two inputs. For adder 1, there is obviously no carry input but instead two data inputs. For adder 3 there is a carry input (coming from adder 2) and a single data input. For adder 4 there is a carry input (coming from adder 3) and a single data input. And finally for adder 5, there is a carry input (coming from adder 4) and a single data input.
Now many of you might be thinking "Hang on a second, there's actually a lot more data inputs than what was mentioned in the above". This is true, but this is where the pass transistors come into the picture. Remember that the VIC chip takes turn about fetching cell index data from the video matrix memory and then character data. So sometimes it is using the base address for the video memory and sometimes it is using the base address of the character memory. Which one it is currently using is determined by the value of HCC0 (i.e. bit 0 of the Horizontal Cell Counter). When HCC0 is LOW, it is fetching from the video matrix memory, and when HCC0 is HIGH, it is fetching from the character memory. So all those pass transistors across the middle of the logisim image above that are controlled by HCC0 and HCC0' are what let in either the base video matrix address or the base character memory address. So although adder 1 (for example) appears to have four data inputs, only two of them are actually passing through at any one time.
Something similar is happening for the sum outputs of the adders. You will see that each adder sum output (except for adder 5) connects to two different address lines... but not directly. Instead they connect to the two different address lines via two different pass transistors, where one pass transistor is controlled by HCC0 and the other by HCC0'. What this means is that when HCC0 is LOW, the output of the adder connects to one address line, and when it is HIGH, it connects to another address line.
"Why is it doing this?" you may be wondering. At first it doesn't make a lot of sense. The reason can be explained by looking at adder 2 and thinking a bit about why there is only one Full Adder and four half adders. Adder 5 isn't actually doing anything of use when HCC0 is HIGH. The base address value, i.e. the character base address, is only four bits, so to those four bits it needs to add the values of BM10 and BM11. The value of BM9 passes straight through to the inverter immediately before the A9' output and isn't used in any of the adders. The sum outputs of adders 1 to 4 then go to A10' to A13'. In this case, i.e. when HCC0 is HIGH, adder 2 has three inputs, which are the two data inputs (BC11 and BM11) and the carry from adder 1. It is the only adder than has three inputs in this case.
Now let's look at what happens when HCC0 is LOW. All five adders are in use. BV9 is added to VMC10. That is two inputs for adder 1. The carry from adder 1, BV10, and VMC11 are then added together in adder 2. That is once again three inputs for adder 2. But now if we look at adders 3, 4, and 5, they only have two inputs. For adder 3, the inputs are the carry from adder 2 and BV11. For adder 4, the inputs are the carry from adder 3 and BV12. And finally for adder 5, the inputs are the carry from adder 4 and BV13.
When HCC0 is LOW, adder 2 (the Full Adder) is calculating bit 10 of the address line output, and when HCC0 is HIGH, adder 2 is calculating bit 11 of the address line output. It is only in those two cases where a full adder is required. So it seems to be that in order to save space, and to require only one Full Adder, they've made use of these pass transistors so that BV10 goes into adder 2 when HCC0 is LOW, but BC11 goes into adder 2 when HCC0 is HIGH, and the other inputs shift one way or the other as appropriate.
Last edited by lance.ewing
on Sat Jan 13, 2018 12:30 pm, edited 1 time in total.