SuperCPU for the Vic-20

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Schlowski
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Re: SuperCPU for the Vic-20

Postby Schlowski » Wed May 17, 2017 12:03 pm

Ah, this is so clever - I needed a few moments to understand your concept, basically you created a sort of port or I/O registers from 65C02 to 6502 with an address and a data port. A little bit like the C128 talks to its VDC, if I think about this.

My first idea was to reserve a backbuffer in 65C02 memory which acts as screen memory and let the 6502 copy that memory in a neverending loop to the VIC. Something like this (untested, direkt brain to keyboard assembly :lol: )

Code: Select all

ForEver:
   lda   #<Buffer
   sta   $FA
   lda   #>Buffer
   sta   $FB
   lda   #<VICScreen
   sta   $FC
   lda   #>VICScreen
   sta   $FD
   ldx   #4
OuterLoop:   
   ldy   #0
InnerLoop:   
   lda   ($FA),y
   sta   ($FC),y
   dey
   bne   InnerLoop
   inc   $FB
   inc   $FD
   dex
   bne   OuterLoop
   jmp   ForEver
   


This way the 65C02 would have a more traditional screen to write to.
Thinking about my snippet, it would need another copy loop for the color ram, so maybe (or not so maybe but surely) this isn't the fastest solution.

Btw. your new memory layout sounds great with a maximum of shared memory and separate zeropages and stacks. I'm really looking forward to experiment with this board!

Edit: Just saw Eslapions post, especially
It seems to me the 65C02 also doesn't have access to the 656X and 6522 registers so the MOS 6502 has to manage that for the 65C02.

That reminds me that for transferring key or joystick input the 6502 must stash these infos in corresponding "mailbox slots" in the $2000 - $7FFF area so the 65C02 could poll for input

KilrPilr
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Re: SuperCPU for the Vic-20

Postby KilrPilr » Wed May 17, 2017 12:07 pm

Sounds pretty cool. Count me in for 2, of course depending on price. Thanks

What are you going to call it? VC=MHZ20? or maybe MegaC=V20Hertz ?

Or maybe just "MACHV20"? Yeah I like that the best :)

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Kakemoms
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Re: SuperCPU for the Vic-20

Postby Kakemoms » Wed May 17, 2017 12:27 pm

Schlowski wrote:No wishful thinking on my side, I simply wanted to clarify that Eslapions 4K dual port SRAM would mean a mainboard modification which is not part of this project. Maybe my wording wasn't clear enough...


There is only a cartridge to plug into the expansion port, nothing else. No soldering or modifications.

And as Eslapion points out, the internal 6502 becomes a kind of memory management unit for the system.

KilrPilr wrote:Sounds pretty cool. Count me in for 2, of course depending on price. Thanks


Price is going to be as low as possible. The second run may be larger if we bring this home. I will put aside two for you.

At the moment 5 are still available. No payment until I have them finished and tested as I don't know the price. I will update progress here.

Edit:
Schlowski wrote:That reminds me that for transferring key or joystick input the 6502 must stash these infos in corresponding "mailbox slots" in the $2000 - $7FFF area so the 65C02 could poll for input


That is the safe way to exchange data. Now, for screen data updates one doesn't need to transfer the whole screen, only bytes that change. So my previous estimate of 22K cycles for 190*160 pixels is really just the worst case. For example - most 3D objects would only cover a part of the screen and could be updated faster.

Given a full 64KB page (once I put in more memory), most of the system could be emulated by the 65C02 in that page. I/O would still require some tweaking to get going, but many games may run fine without too much patching. For example Chess and other board games.

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Re: SuperCPU for the Vic-20

Postby eslapion » Wed May 17, 2017 1:30 pm

@Kakemoms
I feel left out...

eslapion wrote:Also, if the MachXO3L is the better solution, how do the CPUs behave when both are accessing RAM between $2000-$5FFF ? Dual port RAM can manage it but how does the MachXO3L's RAM react ?

Pretty please tell me what's going to happend...
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Re: SuperCPU for the Vic-20

Postby Kakemoms » Thu May 18, 2017 3:59 pm

eslapion wrote:@Kakemoms
I feel left out...

eslapion wrote:Also, if the MachXO3L is the better solution, how do the CPUs behave when both are accessing RAM between $2000-$5FFF ? Dual port RAM can manage it but how does the MachXO3L's RAM react ?

Pretty please tell me what's going to happend...


Sorry, there was just so many posts here that I didn't manage to go through it all. I also need to get the layout done, so there will be some lag to my responses hereafter.

Anyway, the XO3 can emulate (or what you call it) a true dual port RAM to prevent conflict. The other way is to multiplex. Since the internal RAM runs fine up to 400MHz, there really isn't any wait states in either case.

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Re: SuperCPU for the Vic-20

Postby eslapion » Thu May 18, 2017 4:38 pm

Kakemoms wrote:... the XO3 can emulate (or what you call it) a true dual port RAM to prevent conflict. The other way is to multiplex. Since the internal RAM runs fine up to 400MHz, there really isn't any wait states in either case.

Thanks for the info.

The official name I found on Digikey is "Asynchronous Dual Port SRAM".

The fact the RAM runs at 400MHz doesn't change much. The real issue is that the MOS 6502 ties down the bus for 450-500ns every time it accesses a specific address location. If it tries to access a memory address from a memory chip shared by a much faster CPU then this faster CPU will be prohibited access to its bus for this period of time which is quite long considering the higher speed.

Async DP-SRAM can have 2 different processors (or devices) access the same addresses at different speeds with no bus access problems. In the past, this type of memory was prohibitively expensive and it's price remains quite high but the VIC-20 being what it is, only a small amount could be required for any project related to it.
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Kakemoms
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Re: SuperCPU for the Vic-20

Postby Kakemoms » Fri May 19, 2017 5:28 am

eslapion wrote:The real issue is that the MOS 6502 ties down the bus for 450-500ns every time it accesses a specific address location. If it tries to access a memory address from a memory chip shared by a much faster CPU then this faster CPU will be prohibited access to its bus for this period of time which is quite long considering the higher speed.


In theory, but not in a CPLD/FPGA. There are buffers that handle input and output, so the actual memory access happends in one cycle either way. Thus, even if the MOS 6502 is slow and one has to wait for the data (address arrives first), no access into the memory is done before both have been supplied and the internal code can then put it into the internal RAM (during write). This is the same for the reading; address arrives first, memory is read, then put onto the output buffer of the CPLD so that it can feed the MOS 6502 at its own slow pace. You can think of it as a FIFO buffer.

eslapion wrote:Async DP-SRAM can have 2 different processors (or devices) access the same addresses at different speeds with no bus access problems. In the past, this type of memory was prohibitively expensive and it's price remains quite high but the VIC-20 being what it is, only a small amount could be required for any project related to it.


That is true, so even if I tried the muliplexing first, it was easier to just use the internal dual port ram and forget about multiplexing. But when I increase the RAM size by external RAM, it will be accessed using the previous mentioned multiplexing.

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beamrider
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Re: SuperCPU for the Vic-20

Postby beamrider » Fri May 19, 2017 7:03 am

I would be interested in one of these please.

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Re: SuperCPU for the Vic-20

Postby eslapion » Fri May 19, 2017 1:06 pm

Kakemoms wrote:That is true, so even if I tried the muliplexing first, it was easier to just use the internal dual port ram and forget about multiplexing. But when I increase the RAM size by external RAM, it will be accessed using the previous mentioned multiplexing.

I believe you mentioned another version of the MachXO3 will soon come on the market with considerably more available memory.
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Re: SuperCPU for the Vic-20

Postby pixel » Sat May 20, 2017 2:34 am

If I hadn't had so much on my plate already (Arukanoido, Ultimem, tapesondemand.com, etc.) I'd jump right in.

That copying loop is really refreshingly clever but let's talk applications. Moving memory that way is still spoiling the fun. Any chance to wedge in hardware copy? EDIT: Even if it was only whole pages?
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Mike
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Re: SuperCPU for the Vic-20

Postby Mike » Sat May 20, 2017 2:49 am

pixel wrote:If I hadn't had so much on my plate already (Arukanoido, Ultimem, tapesondemand.com, etc.) I'd jump right in.

That copying loop is really refreshingly clever but let's talk applications. Moving memory that way is still spoiling the fun. Any chance to wedge in hardware copy? EDIT: Even if it was only whole pages?

For all intents and purposes, that unrolled copy loop is identical to the method tokra and I used to construct the new graphic modes (by having a 'distributed' bitmap in the immediate operand field of LDA instructions), and the fast transfer routines proposed by TLovskog (SD-Card to VIC mem) for his GCart 2011.

I just mentioned on the first page of this thread, that using the internal CPU this way is the only method to transfer data from the expansion port to the internal memory of the VIC-20 and, once again, no amount of wishful thinking is going to change that. The combo LDA #imm:STA abs (with 6 cycles/byte) is the fastest practicable way - sorting the values and only doing one LDA #imm for several STAs would approach 4 cycles/byte, but would incur a lot of extra processing by the external CPU beforehand.

Even with 'just' 6 cycles/byte, a 160x192 MINIGRAFIK bitmap could be updated nearly once per frame (3840 bytes => 23040+X cycles and a PAL frame has 312x71 = 22152 cycles) and if one insists on a more practical memory layout, an unrolled LDA abs,X:STA abs,X loop still works at 9 cycles/byte. More than fast enough for normal text screens.

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pixel
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Re: SuperCPU for the Vic-20

Postby pixel » Sat May 20, 2017 3:17 am

Mike wrote:I just mentioned on the first page of this thread, that using the internal CPU this way is the only method to transfer data from the expansion port to the internal memory of the VIC-20 and, once again, no amount of wishful thinking is going to change that.

Oops. Sorry. Thank you for elaborating.
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Mike
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Re: SuperCPU for the Vic-20

Postby Mike » Sat May 20, 2017 3:19 am

pixel wrote:Oops. Sorry. Thank you for elaborating.

Just think about the VIC-20 being an intelligent graphics adapter for the external CPU. ;)

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Re: SuperCPU for the Vic-20

Postby pixel » Sat May 20, 2017 5:11 am

Mike wrote:Just think about the VIC-20 being an intelligent graphics adapter for the external CPU. ;)

Dude, am doing that already. ;) But I have to ignore this project till the other stuff is finished.
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Re: SuperCPU for the Vic-20

Postby Vic20-Ian » Sun May 21, 2017 12:30 pm

Audio-Computers advertised a 40 Column card with 2nd processor (Intel 8088). 8K Ram and can communicate with 2nd processor via 2k dual port ram.

I have a scan of the advert, if anyone wants it send a PM.
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