VicDust

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Kakemoms
Vic 20 Afficionado
Posts: 428
Joined: Sun Feb 15, 2015 8:45 am

VicDust

Postby Kakemoms » Sat Feb 11, 2017 5:42 pm

After a too long delay I finally got some hardware together and now have a (running) Lattice CPLD attached to the Vic-20 expansion port:
image.jpeg


This was originally about making a 65C02 based unit, but I have other plans for it as well.

Current state is not completely working, but I am able to get the Vic-20 to write to its memory. Some timing issue remains on the read side. Both write & read happends at 133MHz..

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Kakemoms
Vic 20 Afficionado
Posts: 428
Joined: Sun Feb 15, 2015 8:45 am

Re: VicDust

Postby Kakemoms » Sat Mar 11, 2017 4:23 am

Just a short update to this tedious project;-)

I have been hacking away on the CPLD which is both fun and frustration in one package. First I thought I could use clk2 to control everything, but I have settled on using the internal fpga clock and other signals to get a proper response. The reason is that the interpreter doesn't like external clocks, and due to the slow Vic-20 bus its no point to use that anyway.

As for most old hardware, there are variations in timing and signal, which is actually what is causing most problems right now. Especially the need to grab and release the databus to prevent confusion (and false data) is not straightforward, but needs precise timing. Anyone who has worked with the C64 PLA knows what I am talking about.

So this is how I do it:
I use an internal fpga clock and combine it with a counter. Thus, I can measure out a Vic-20 clock cycle without involving any 6502 signals.
I use the address lines to syncronize the clock. E.g. I look for when the address changes and set that as start of the clock cycle.
I get the CPLD to fetch data or respond by pushing data according to BLK/RAM/CRW signals.

It sounds straightforward, but its not. Once I get everything stable I will put it into a schematics and test it out as a PCB. It will include a CPLD capable of 6502/65816, a VGA output, DDR memory and some custom IO ports to play with.

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Kakemoms
Vic 20 Afficionado
Posts: 428
Joined: Sun Feb 15, 2015 8:45 am

Re: VicDust

Postby Kakemoms » Fri Mar 17, 2017 2:24 pm

I am happy to say that I at least got the Vic-20 to Lattice MachXO3 logic working.

For now, its only acting as a memory expander, but it was still an achievement to get it working (while I was learning Verilog in the process) :mrgreen:

Vic-20-MachXO3-RAM-expansion.png


The OBS window above is my Vic-20 video output (captured and shown on the PC screen).

Internally, the memory access is done at 33MHz (I slowed it down a little). It should be able to reach around 100MHz without the debug logic.

Next step is to include a 6502 core in the MachXO3.


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