Denial

At blooming last! Spot on, you two - fetching one CPU cycle earlier fixes the artefacts1 my_tiger.png Now all I've got left is sound and lightpen. Nice work! VIC-I sound is kind of fiddly, especially the noise channel. Nippur72 did some previous FPGA work on this referenced somewhere here: thread ....

Yet you would preferably use open-collector or open-drain outputs for that. mmmh doesnt "NMOS" imply "open-collector"? You can have push-pull, see p3 here: https://www.princeton.edu/~mae412/HANDOUTS/Datasheets/6522.pdf It's just that most of it is open-drain with an NMOS transis...

Several bus signals cause the luma to slightly decrease - see this picture (much exaggerated for demonstration of course). In the vic20 there is probably similar stuff happening. Come to think of it, I believe border color in the screen area using MC mode is different from BG color i MC mode side b...

JonBrawn wrote: ↑Thu Oct 13, 2022 11:47 pmOK, so... I'll solder a 100uF capacitor onto each of the data lines!

Are you sure?

It looks like the FPGA is occasionally reading "bum data," as we industry professionals call it, from memory and getting $FF instead of the correct value. My current thinking is that the pull-up resistors and relatively high capacitance of the cheapo FETs I'm using as level shifters make ...

Cool, thanks, i added them to the testrepo. Also the odd/even lines seem to be correct in VICE. The colors themselves are still a bit off here and there... *sigh* My experience is that colors look slightly different depending on which type they are. Background colors are slightly off from the same ...

It does not measure color ram fetch latency though. The colour RAM shares its address pins with the lower 10 bits of the VA address bus. The colour RAM data thus is fetched exactly in the same cycle as the screen codes, in parallel. VIC-I reads the screen codes over BD0..BD7 (pins 16..9) and the co...

In general, all those screenmodes dynamically update character generator data and colour RAM data as the beam races the screen, ensuring that the necessary data is right 'there' in internal RAM when the VIC chip wants to fetch it. Sometimes the correct data arrives in RAM in the cycle before VIC do...

In general, all those screenmodes dynamically update character generator data and colour RAM data as the beam races the screen, ensuring that the necessary data is right 'there' in internal RAM when the VIC chip wants to fetch it. Sometimes the correct data arrives in RAM in the cycle before VIC do...

This is the NTSC version - however, I have a PAL Vicky 20 with a 6561 and a TV that can display PAL, so that is the direction I'll be heading in next. However, I want to get the NTSC version finished before I start on that. The reason I asked is that there are probably more (test) programs targetin...

JonBrawn wrote: ↑Tue Oct 04, 2022 8:50 pm So, I think I might have finished with the video section. Other than TEST7A, TEST8A and TIMING_NTSC, are there any other test programs that I should be running to confirm that it's doing the right thing?

Is this strictly NTSC or is PAL also implemented?

That is... interesting... damned difficult to achieve, but interesting. What I currently have for the fetch and colour generation logic is all clocked by the phi1 and phi2 clocks, from which you can't get a single pixel delay, so somewhere there's some oddity in there pixel shift register - possibl...

If you are running periodic NMI's in your code I find that the KERNAL reset code sometimes locks up, hence the added disabling of VIA interrupts. Because the primary vector in the KERNAL is just set to jump to a vector in page 3 if an NMI goes off before (or while) the vector is written by the cold...

OK, a "custom" restart is wanted here. FWIIW, since the VIC did not come standard with a hardware reset, I was never a fan of games not allowing for a soft reset that would return the machine back to normal control. And the built-in Run/Stop RESTORE was no guarantee after the better games...

I wrote some test programs when tweaking the vice implementation, here: https://sourceforge.net/p/vice-emu/code/HEAD/tree/testprogs/VIC20/split-tests/ Try timing. It tries to sample those registers for every cycle and allow you to save the result as a file. Could you explain the format of the tmdum...